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參數(shù)資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數(shù)： | 83/92頁 |
| 文件大?。?/td> | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Rev. 0 | Page 83 of 92
Address
A6
A7
A8
A9
AA
Data
Bits
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[12:0]
[25:13]
[0]
[1]
[2]
[3]
Default
Value
0
0
0
0
0
0
0
0
0
0
0
0
Update
Type
VD
VD
VD
VD
VD
VD
VD/SG
VD/SG
Name
GP8_TOG2_LN
GP8_TOG2_PX
GP8_TOG3_FD
GP8_TOG3_LN
GP8_TOG3_PX
GP8_TOG4_FD
GP8_TOG4_LN
GP8_TOG4_PX
SUBCK_TOG1_13
SUBCK_TOG2_13
SUBCKHP_TOG1_13
SUBCKHP_TOG2_13
Description
General-Purpose Signal 8, second toggle position, line location.
General-Purpose Signal 8, second toggle position, pixel location.
General-Purpose Signal 8, third toggle position, field location.
General-Purpose Signal 8, third toggle position, line location.
General-Purpose Signal 8, third toggle position, pixel location.
General-Purpose Signal 8, fourth toggle position, field location.
General-Purpose Signal 8, fourth toggle position, line location.
General-Purpose Signal 8, fourth toggle position, pixel location.
Bit [13] for SUBCK Toggle Position 1. For 14-bit H-counter mode.
Bit [13] for SUBCK Toggle Position 2. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 1. For 14-bit H-counter mode.
Bit [13] for SUBCK HP Toggle 2. For 14-bit H-counter mode.
Table 37. Update Control Registers
Data
Bits
B0
[15:0] 1803
Address
Default Value Update Name
SCK
Description
Each bit corresponds to one address location.
AFE_UPDT_SCK [0] = 1, update Address 0x00 on SL rising edge.
AFE_UPDT_SCK [1] = 1, update Address 0x01 on SL rising edge.
…
AFE_UPDT_SCK [15] = 1, update Address 0x0F on SL rising edge.
Each bit corresponds to one address location.
AFE_UPDT_VD [0] = 1, update Address 0x00 on VD rising edge.
AFE_UPDT_VD [1] = 1, update Address 0x01 on VD rising edge.
…
AFE_UPDT_VD [15] = 1, update Address 0x0F on VD rising edge.
Enable SCK update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable VD update of miscellaneous registers,
Address 0x10 to Address 0x1F.
Enable SCK update of VDHD registers, Address 0x20 to Address 0x2F.
Enable VD update of VDHD registers, Address 0x20 to Address 0x2F.
AFE_UPDT_SCK
B1
[15:0] E7FC
SCK
AFE_UPDT_VD
B2
[15:0]
F8FD
SCK
MISC_UPDT_SCK
B3
[15:0]
0702
SCK
MISC_UPDT_VD
B4
B5
[15:0]
[15:0]
FFF9
0006
SCK
SCK
VDHD_UPDT_SCK
VDHD_UPDT_VD
Table 38. Extra Registers
Address
Data Bits
D4
[0]
[1]
[9:2]
D7
[0]
[1]
Default Value
0
0
0
0
0
Update
SCK
SCK
Name
TEST
GPO_INT_EN
TEST
TEST
XV24_SWAP
Description
Test use only. Set to 0.
Allow observation of internal signals at GPO5 to GPO8 outputs.
GPO5: OUTCONTROL.
GPO6: HBLK.
GPO7: CLPOB.
GPO8: PBLK.
Test use only. Set to 0.
Test use only. Set to 0.
Set to 1 to change the V-driver output configuration so that XV15 is
output on the XV24 output pin. Useful with special vertical
sequence alternation mode when the XV24 register is reserved for
pattern selection.
Recommended start-up register. Should be set to 0x888.
D8
[27:0]
0
SCK
START
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