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參數(shù)資料
| 型號(hào)： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁(yè)數(shù)： | 77/92頁(yè) |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Rev. 0 | Page 77 of 92
Address
15
Data
Bits
[0]
Default
Value
0
Update
Type
SCK
Name
OSC_RSTB
Description
CLO oscillator reset bar.
0: oscillator in power-down state; 1: resume oscillator
operation.
Test mode only. Must be set to 0.
Serial update line.
Sets the line (HD) within the field to update the VD-updated
registers.
Prevents the update of the VD-updated registers.
0: normal update; 1: prevent update of VD-updated registers.
1: enable reset of the shutter control after SYNC operation
occurs.
1: forces shutter control to reset.
1: reset shutter and GPO control at SYNC operation.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0.
Test mode only. Must be set to 0xA.
Each bit selects XV pulses for use as VSG pulses.
VSG masking. Overrides settings in field registers when
enabled.
0: disable VSGMAK_CTL bits. VSG masking is controlled by field
registers.
1: enable VSGMASK_CTL bits to control VSG masking
1: enable 14-bit H-counter.
1: disable clamp operation if PBLK is active at the same time as
CLPOB.
16
17
[27:0]
[12:0]
0
0
SCK
SCK
TEST
UPDATE
[13]
0
PREVENTUP
[14]
0
SYNC_RST_SHUTEN
18
19
1A
1B
1C
1D
[15]
[16]
[27:0]
[27:0]
[27:0]
[27:0]
[23:0]
[23:0]
0
0
0
0
0
A
FF0000
0
SCK
SCK
SCK
SCK
SCK
SCK
REG_RST_SHUT
GPO_RST_SYNC
TEST
TEST
TEST
TEST
VSGSELECT
VSGMASK_CTL
[24]
0
VSGMASK_CTL_EN
1F
[0]
[1]
1
1
SCK
HCNT14_EN
PBLK_MASK_EN
Table 30. VD/HD Registers
Address
Data Bits
20
[0]
21
[0]
22
[12:0]
[25:13]
Default Value
0
0
0
0
Update Type
SCK
VD
VD
Name
MASTER
VDHDPOL
HDRISE
VDRISE
Description
VD/HD master or slave mode. 0: slave mode; 1: master mode.
VD/HD active polarity. 0 = low, 1 = high.
Rising edge location for HD. Minimum value is 36 pixels.
Rising edge location for VD.
Table 31. I/O and Charge Pump Registers
Data
Bits
Value
23
[0]
0
Address
Default
Update
Type
SCK
Name
OSC_NVR
Description
Oscillator normal voltage range. Set to match CLIVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
XV output normal voltage range. Set to match XVVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
I/O normal voltage range. Set the match IOVDD supply voltage.
0 = 1.8 V, 1 = 3.3 V
Data pin normal voltage range. Set to match DRVDD supply voltage.
0 = 1.8 V I/O, 1 = 3.3 V I/O.
Test use only. Set to 0.
Test use only. Set to 0.
1: internal regulator enable for 3.2 V output.
Selects HCLK output configuration. Should be written to desired value.
001 = Mode 1, 010 = Mode 2, 100 = Mode 3. All other values are invalid.
[1]
0
XV_NVR
[2]
0
IO_NVR
[3]
0
DATA_NVR
[4]
[5]
[6]
[9:7]
0
0
0
1
TEST
TEST
LDO_32_EN
HCLKMODE
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