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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 80/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Rev. 0 | Page 80 of 92
Address
Data
Bits
[13:6]
Default
Value
0
Update
Type
Name
MANUAL_TRIG
Description
6: SLR read (manual).
7: force to idle.
1: manual trigger for GP signals, when Protocol 1 is selected.
Bit [6] : GP1 manual trigger
…
Bit [13] : GP8 manual trigger
Primary counter maximum value.
Secondary counter maximum value.
Mask VD/HD during counter operation.
Number of fields to delay before the next count (exposure) starts.
ShotTimer with RapidShot, skip delay before first count (exposure).
Number of fields to delay before the next count starts.
ShotTimer with RapidShot, skip delay before first count.
Selects protocol for each general-purpose signal.
Idle = 0.
No counter association = 1.
Link to primary = 2.
Link to secondary = 3.
Link to mode = 4.
Primary repeat = 5.
Secondary repeat = 6.
Keep on = 7.
Exposure: number of fields to mask SGs.
Exposure plus readout: number of fields to mask SUBCK.
0: SUBCK toggles (Register 0x77) updated on SG line.
1: SUBCK toggles (Register 0x77) updated on UPDATE line (VD-updated)
Skip the SUBCK mask for the first exposure field only. Typically set to 1.
Reserved for test purpose. Must be set to 0.
Line location after VSG line to begin SUBCK pulses.
Must not be set to 1.
Number of SUBCK pulses per field. Must be set less than VDLEN.
Suppress the SG and allow SUBCK to finish at SUBCKNUM.
SUBCK Toggle Position 1.
SUBCK Toggle Position 2.
SUBCK start polarity.
Hi-Precision SUBCK Toggle Position 1.
Hi-Precision SUBCK Toggle Position 2.
GP1 low/high start polarity.
GP2 low/high start polarity.
GP3 low/high start polarity.
GP4 low/high start polarity.
GP5 low/high start polarity.
GP6 low/high start polarity.
GP7 low/high start polarity.
GP8 low/high start polarity.
1 = GP1 signal is selected for GPO1 output.
1 = GP2 signal is selected for GPO2 output.
1 = GP3 signal is selected for GPO3 output.
1 = GP4 signal is selected for GPO4 output. 0 = SUBCK is selected.
1 = GP5 signal is selected for GPO5 output. 0 = XV21 is selected.
71
72
[12:0]
[24:13]
[27:25]
[12:0]
0
0
0
0
VD
VD
PRIMARY_MAX
SECOND_MAX
VDHD_MASK
PRIMARY_DELAY
[13]
0
PRIMARY_SKIP
73
[26:14]
[27]
[2:0]
[5:3]
[8:6]
[11:9]
[14:12]
[17:15]
[20:18]
[23:21]
0
0
0
0
0
0
0
0
0
0
VD
SECOND_DELAY
SECOND_SKIP
GP1_PROTOCOL
GP2_PROTOCOL
GP3_PROTOCOL
GP4_PROTOCOL
GP5_PROTOCOL
GP6_PROTOCOL
GP7_PROTOCOL
GP8_PROTOCOL
74
[12:0]
[25:13]
[26]
0
0
1
VD
SGMASK_NUM
SUBCKMASK_NUM
SUBCKTOG_UPDATE
75
[27]
[0]
[13:1]
0
0
0
SG
SUBCKMASK_SKIP1
TEST
SUBCKSTARTLINE
76
77
78
[26:14]
[27]
[12:0]
[25:13]
[26]
[12:0]
[25:13]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
0
0
1FFF
1FFF
0
1FFF
1FFF
0
0
0
0
0
0
0
0
1
1
1
1
1
VD
VD/SG
VD
SUBCKNUM
SG_SUPPRESS
SUBCK_TOG1
SUBCK_TOG2
SUBCK_POL
SUBCKHP_TOG1
SUBCKHP_TOG2
GP1_POL
GP2_POL
GP3_POL
GP4_POL
GP5_POL
GP6_POL
GP7_POL
GP8_POL
SEL_GP1
SEL_GP2
SEL_GP3
SEL_GP4
SEL_GP5
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
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