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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 55/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
GP LOOK-UP TABLES (LUT)
The AD9992 is equipped with a look-up table for each pair of
consecutive GP signals when configured as outputs. GP1 is
always combined with GP2, GP3 is always combined with GP4,
GP5 is always combined with GP6, and GP7 is always combined
with GP8. The external GPO outputs from each pair can output
the result of the LUT or the original GP internal signal.
Rev. 0 | Page 55 of 92
GP1
LUT
1
0
0
1
GPO2
GPO1
GP2
GP2_USE_LUT
GP1_USE_LUT
0
Figure 62. Internal LUT for GP1 and GP2 Signals
Address 0x79 dictates the behavior of the LUT and which
signals receive the result. Each 4-bit LUT_FOR_GPxy register
can realize any logic combination of GPx and GPy. For example,
Table 23 shows how the register values of LUT_FOR_GP12 [11:8]
are determined. XOR, NAND, AND, and OR results are shown,
but any 4-bit combination is possible. A simple example of XOR
gating is shown in Figure 63.
Table 23. LUT Results Based on GP1, GP2 Values
GP2
GP1
LUT: XOR
0
0
0
0
1
1
1
0
1
1
1
0
LUT_FOR_GP12[11:8] = 0x06
GP2_USE_LUT = 1 GP1_USE_LUT = 0
LUT: NAND
1
1
1
0
LUT: AND
0
0
0
1
LUT: OR
0
1
1
1
GP1
GP2
GPO2
NOTES
1. LOGIC COMBINATION (XOR) OF PROGRAMMED TOGGLES
GP1AND GP2.
GPO1
0
Figure 63. LUT Example for GP1 XOR GP2
Field Counter and GPO Limitations
The following is a summary of the known limitations of the
field counters and GPO signals that dictate usability.
The field counter trigger (PRIMARY_ACTION and
SECONDARY_ACTION registers, Address 0x70) is self-reset
at the start of every VD period. Therefore, there must be one
VD period between sequential programming to that address.
If GP*_PROTOCOL = 1, it must be manually reset to
GP*_PROTOCOL = 0 one VD period before it can be
used again. If manual toggles are desired in sequential fields,
the MANUAL_TRIG register should be used in conjunction
with GP*_PROTOCOL = 1.
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相關代理商/技術參數 |
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
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