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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 67/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
Rev. 0 | Page 67 of 92
VD
HD
CLI
X
X
X
X
X
X
X
X
3ns MIN
X
X
X
X
X
X
X
X
X
X
X
X
X
3ns MIN
t
CLIDLY
35.5 CYCLES
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
1
2
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, AND THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 35.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 36 OR 37 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHDLOC = 0 IS SHOWN IN ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 36 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN FIVE CLI CYCLES PRIOR TO THE VD FALLING EDGE.
Figure 75. External VD/HD and Internal H-Counter Synchronization, Slave Mode
H-COUNTER
RESET
SHD
INTERNAL
HD
INTERNAL
H-COUNTER
(PIXEL COUNTER)
t
VDHD
0
1
HBLKTOG1
2
HBLKTOG2
3
CLPOB_TOG1
4
CLPOB_TOG2
60
100
103
112
(60 – 36) = 24
(100 – 36) = 64
(103 – 36) = 67
(112 – 36) = 76
MASTER MODE
SLAVE MODE
H1
CLPOB
PIXEL NO.
HD
112
103
100
60
0
1
2
3
4
0
Figure 76. Example of Slave Mode Register Setting to Obtain Desired Toggle Positions
Vertical Toggle Position Placement Near Counter Reset
An additional consideration during the reset of the internal
counters is the vertical toggle position placement. Prior to the
internal counters being reset, there is a region of 36 pixels
during which no toggle positions should be programmed.
As shown in Figure 77, for master mode the last 36 pixels before
the HD falling edge must not be used for toggle position placement
of the V, VSG, SUBCK, HBLK, PBLK, or CLPOB pulses.
Figure 78 shows the same example for slave mode. The same
restriction applies: the last 36 pixels before the counters are
reset cannot be used. However, in slave mode, the counter reset
is delayed with respect to VD/HD placement, so the inhibited
area is different than it is in master mode.
It is recommended that Pixel Location 0 not be used for any of
the toggle positions for the VSG and SUBCK pulses.
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相關代理商/技術參數 |
參數描述 |
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
| AD9993BBCZRL | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:帶卷（TR） 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1,500 |
| AD9993-EBZ | 功能描述:EVAL BOARD MXFE AD9993 制造商:analog devices inc. 系列:* 零件狀態:在售 標準包裝:1 |
| AD9994 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
| AD9994BCP | 制造商:Analog Devices 功能描述:AFE GEN PURPOSE 12-BIT 64LFCSP - Bulk |
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