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參數資料
| 型號： | AD9992BBCZRL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | 12-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA105 |
| 封裝： | 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105 |
| 文件頁數： | 64/92頁 |
| 文件大小： | 718K |
| 代理商： | AD9992BBCZRL |
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AD9992
POWER-UP SEQUENCE FOR MASTER MODE
When the AD9992 is powered up, the following sequence is
recommended (refer to Figure 73 for each step). Note that a
SYNC signal is required for master mode operation. If an
external SYNC pulse is not available, it is possible to generate an
internal SYNC event by writing to the SWSYNC register.
Rev. 0 | Page 64 of 92
1.
Turn on the power supplies for AD9992 and start the
master clock, CLI.
Reset the internal AD9992 registers by writing 1 to the
SW_RST register (Address 0x10).
By default, Vertical Outputs V1 to V24 are low. If
necessary, write to the Standby3 output polarity
(Address 0x26) to set different polarities for the vertical
outputs in order to avoid damage to the V-driver
and CCD. Write to Address 0x1C to configure each
V-output as a vertical transfer clock (XV) or sensor
pulse (VSG).
Power-up the V-driver supplies, VH and VL, anytime after
Step 3 is complete to set the proper polarities.
Load the required registers to configure the necessary
vertical timing, horizontal timing, high speed timing,
and shutter timing. Set the recommended start-up
Address 0xD8 to 0x888.
2.
3.
4.
5.
6.
To place the part into normal power operation, write 0x04
to register 0x00. This sets the STANDBY register (AFE
Register Address 0x00, Bits [1:0]) to normal operation and
enables the OB clamp (AFE Register Address 0x00, Bit [2]).
If the CLO output is being used to drive a crystal, also power
up the CLO oscillator by writing 1 to Address 0x15.
By default, the internal timing core is held in a reset state,
with TGCORE_RSTB register = 0. Write 1 to the
TGCORE_RSTB register (Address 0x14) to start the
internal timing core operation. Note if a 2× clock is used
for the CLI input, the CLIDIVIDE register (0x0D) should
be set to 1 before resetting the timing core.
Configure the AD9992 for master mode timing by writing 1
to the MASTER register (Address 0x20).
Write 1 to the OUTCONTROL register (Address 0x11).
This allows the outputs to become active after the next
SYNC rising edge. Normally OUTCONTROL takes effect
after the next VD edge; however, because the part is just
being powered up, there is no VD edge until the rising
edge of the SYNC signal.
10.
Generate a SYNC event. If SYNC is high at power-up,
bring the SYNC input low for a minimum of 100 ns, and
then bring SYNC high again. This causes the internal
counters to reset and starts VD/HD operation. The first
VD/HD edge allows VD-updated register updates to
occur, including OUTCONTROL to enable all outputs.
If a hardware SYNC is not available, the SWSYNC register
(Address 0x13, Bit [14]) can be used to initiate a SYNC event.
7.
8.
9.
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| AD9993BBCZ | 功能描述:IC MIXED-SIGNAL FRONT END 196BGA 制造商:analog devices inc. 系列:- 包裝:托盤 零件狀態:在售 類型:ADC，DAC 輸入類型:LVDS 輸出類型:LVDS 接口:SPI 電流 - 電源:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:196-LFBGA，CSPBGA 供應商器件封裝:196-CSPBGA（12x12） 標準包裝:1 |
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