
GS1559 Data Sheet
30572 - 4
July 2005
19 of 74
Serial Output Intrinsic
Jitter
t
IJ
Pseudorandom and
pathological HD
signal
–
90
125
ps
5
3
Pseudorandom and
pathological SD
signal
–
270
350
ps
5
3
Parallel Output
Parallel Clock
Frequency
f
PCLK
–
13.5
–
148.5
MHz
4
–
Parallel Clock Duty
Cycle
DC
PCLK
–
40
50
60
%
4
–
Output Data Hold
Time
t
OH
20-bit HD, 15pF
1.0
–
–
ns
4
–
10-bit SD, 15pF
19.5
–
–
ns
8
–
Output Data Delay
Time
t
OD
20-bit HD, 15pF
–
–
4.5
ns
4
–
10-bit SD, 15pF
–
–
22.8
ns
8
–
Output Data Rise/Fall
Time
tr/tf
–
–
–
1.5
ns
3
–
GSPI
GSPI Input Clock
Frequency
f
SCLK
–
–
–
6.6
MHz
8
–
GSPI Input Clock Duty
Cycle
DC
SCLK
–
40
–
60
%
8
–
GSPI Input Data
Setup Time
–
–
0
–
–
ns
8
–
GSPI Input Data Hold
Time
–
–
1.43
–
–
ns
8
–
GSPI Output Data
Hold Time
–
–
2.1
–
–
ns
8
–
GSPI Output Data
Delay Time
–
–
–
–
7.27
ns
8
–
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with
guardbands for supply and temperature ranges using correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1, 2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar
product.
9. Indirect test.
NOTES
1. 6MHz sinewave modulation.
2. HD = 1080i, SD = 525i
3. Serial Digital Output Reclocked (
RC_BYP
= HIGH).
4. See
Device Reset on page 68
,
Figure 4-16
.
Table 2-2: AC Electrical Characteristics (Continued)
T
A
= 0°C to 70°C, unless otherwise shown
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Test
Level
Notes