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參數資料
| 型號： | GS1559-CBE2 |
| 廠商： | Gennum Corporation |
| 英文描述： | GS1559 HD-LINX-TM II Multi-Rate Deserializer with Loop-Through Cable Driver |
| 中文描述： | GS1559的HD - LINX進程，商標第二多速率解串器與環通電纜驅動器 |
| 文件頁數： | 9/74頁 |
| 文件大小： | 686K |
| 代理商： | GS1559-CBE2 |
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GS1559 Data Sheet
30572 - 4
July 2005
9 of 74
C8
YANC
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to indicate the presence of ancillary data in the video stream.
HD Mode (SD/HD = LOW)
The YANC signal will be HIGH when the device has detected VANC or
HANC data in the luma video stream and LOW otherwise.
SD Mode (SD/HD = LOW)
For 20-bit demultiplexed data (20bit/10bit = HIGH), the YANC signal will be
HIGH when VANC or HANC data is detected in the luma video stream and
LOW otherwise.
For 10-bit multiplexed data (20bit/10bit = LOW), the YANC signal will be
HIGH when VANC or HANC data is detected anywhere in the data stream
and LOW otherwise.
D1, E1
DDI1, DDI1
Analog
Input
Differential input pair for serial digital input 1.
D4
IP_SEL
Non
Synchronous
Input
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Used to select DDI1 / DDI1 or DDI2 / DDI2 as the serial digital input signal,
and CD1 or CD2 as the carrier detect input signal.
When set HIGH, DDI1 / DDI1 is selected as the serial digital input and
CD1 is selected as the carrier detect input signal.
When set LOW, DDI2 / DDI2 serial digital input and CD2 carrier detect
input signal is selected.
D5
DVB_ASI
Non
Synchronous
Input /
Output
CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT
Signal levels are LVCMOS/LVTTL compatible.
This pin will be an input set by the application layer in slave mode, and will
be an output set by the device in master mode.
Master Mode (MASTER/SLAVE = HIGH)
The DVB_ASI signal will be HIGH only when the device has locked to a
DVB-ASI compliant data stream. It will be LOW otherwise.
Slave Mode (MASTER/SLAVE = LOW)
When set HIGH in conjunction with SD/HD = HIGH and SMPTE_BYPASS
= LOW, the device will be configured to operate in DVB-ASI mode.
When set LOW, the device will not support the decoding or word alignment
of received DVB-ASI data.
D6
LOCKED
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED signal will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode.
It will be LOW otherwise.
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type
Description
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| GS2905 | 500mA CMOS LDO Voltage Regulator |
| GS2905X15 | 500mA CMOS LDO Voltage Regulator |
| GS2905X18 | 500mA CMOS LDO Voltage Regulator |
| GS2905X25 | 500mA CMOS LDO Voltage Regulator |
| GS2905X33 | 500mA CMOS LDO Voltage Regulator |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS1560 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Voltage Controlled Oscillator |
| GS1560A | 制造商:Gennum Corporation 功能描述: |
| GS1560A_07 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:Dual-Rate Deserializer |
| GS1560A_09 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HD-LINX II Dual-Rate Deserializer |
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