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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 20/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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2
–
4
2.2
2.2.1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
Configuration Register Definitions
Version Register at 00h
29 30 31
28
0 1 1 1 0 0 0 1 0 0
0
1
0
1
0
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0 0
This register uniquely identifies this device to the software. The value is fixed at
7115_38A0
’
h
. This register
is read only.
2.2.2
Data Mover Control Register at 04h
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27
B
29 30 31
28
PACKET PER BLOCK
E
H
A
DMACK
D
A
A
D
D
C
D
S
This register controls the Data Mover port and must be set up before using the port. The power-up reset
value of this register =
0000_0000
’
h
BIT
NUMBER
BIT NAME
FUNCTION
DIR
DESCRIPTION
0
–
11
PACKET PER-
BLOCK
Packets per
Block
R/W
Number of packets per block. A packet is the size of the
data payload and is specified as part of the header. The
data mover logic uses this value to deactivate DMDONE.
This field is only used in transmit mode.
12
ENDSWAP
Endian Swap
R/W
Swap endian. When this bit is set, the quadlet formed by
stacking the DM data will be byte reversed, (i.e. the
quadlet formed by fetching doublet AB01 then
‘
CD02
’
will
be 02CD
–
01AB instead of AB01CD02). In byte mode the
quadlet formed by fetching AB, 01, CD, 0 will be
02CD01AB instead of AB01CD02.
13
BYTEMODE
Byte Mode
R/W
Byte mode. When this bit is set the DM port will only look
at DM0
–
DM7. DM8
–
DM15 will be ignored for transmit
and will not be driven on receive. In this mode, the
maximum speed allowed is 200 Mbps.
14
HANDSHK
Handshake
Mode
(CPLynx
Mode)
R/W
Handshake. When this bit is 1 DMREADY and DMDONE
are in strict handshake mode (i.e., TSB12LV31
compatible mode). DMREADY must not be deactivated
until DMDONE activates. When this bit is set to 0,
DMREADY may be deactivated before DMDONE
activates.
15
AUTOUP
Automatic
Address Up-
date
R/W
Automatic update offset address. Valid only for
asynchronous transmit using header insert mode (bit 27
DMHDR set to 1). For write request asynchronous
packets, header quadlet 2 contains the destination offset
low address for the write. When this bit is set, header
quadlet 2 will be updated by the value of the payload size
(rounded up to the nearest quadlet boundary).
16
–
20
DMACK
DM
Acknowledge
R
DM acknowledge. This is the ack received from the
receiving node. This is updated only when the transfer is
from the DM port.
21
RESERVED
RESERVED
22
–
23
SPEED
DM Speed
Code
R/W
Speed code. This is valid for isochronous transmit and
asynchronous transmit through the DM port. The DM
logic uses this field to specify to the Phy the speed of the
isochronous transfer.
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