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參數(shù)資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數(shù)： | 67/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
11
Table 5
–
1. Modes of Operation
DMRX
0
Isochronous packet transmit with auto header insertion
1
Isochronous packet receive without header and trailer
0
Isochronous packet transmit without header insertion
1
Isochronous packet receive with header and trailer
0
Asynchronous packet transmit with auto header insertion
1
Asynchronous packet receive without headers and trailer
0
Asynchronous packet transmit without header insertion
1
Asynchronous packet receive with headers and trailer
DMASYNC
0
0
0
0
1
1
1
1
DMHDR
0
0
1
1
0
0
1
1
MODE OF OPERATION
5.2.1
Upon receiving a high on DMREADY, the following sequence of operations is performed:
Isochronous Transmit With Automatic Header Insertion
Step 1:
DMDONE will be asserted low (deactivated) at the next DMCLK cycle.
Step 2:
The data mover will take the header that has been loaded into the header0 register at 38h
and request the link core to transmit the data onto the 1394 bus.
Step 3:
The link core will fetch the header from the header0 register.
Step 4:
DMPRE will pulse for one DMCLK cycle before the first data quadlet is sent.
Step 5:
The data mover will then begin to fetch the data payload by asserting DMRW high.
Step 6:
When the link core has fetched the last data quadlet, the data mover checks if the number
of channels specified by the control registers have been sent. If all channels have been sent
the data mover waits for a subaction gap to occur before asserting DMDONE high to
indicate the end of the cycle. Otherwise the data mover will provide the header in the next
header register and then begin fetching the data payload until all channels are complete.
The timing diagrams in Figures 5
–
13 to 5
–
15 illustrate this mode of operation at different transmit speeds.
For simplification, these diagrams show three quadlets of data payload.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
13. Isochronous Transmit With Auto Header Insertion at 400 Mbps
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
14. Isochronous Transmit With Auto Header Insertion at 200 Mbps
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