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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 59/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
3
Bit 0
MSB
LSB
Data Mover Data
DMD0
–
DMD15
1394 Packet Data
. . .Bit 31
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15
Figure 5
–
3. Transmit Data Path
The DM isochronous transmit reads data from the DM interface (DMD[0
–
15] lines) and passes it to the 1394
isochronous transmit interface in accordance with Figure 5
–
2. The data path is shown in Figure 5
–
3. The
asynchronous header registers will contain the latest extracted header from the asynchronous stream when
the header is supplied via the DM port. For automatic header insertion, the
datalength
field in the header
register will be automatically updated by the payload size of the previous asynchronous transmit packet.
This option can be turned off by setting the appropriate bits in the DM control registers. The DM
asynchronous transmit reads data from the DM interface (DMD[0:15] lines) and passes it to the 1394
asynchronous interface in accordance with Figure 5
–
4
Asynchronous DM Idle
(DMDONE is high)
DMEN is 1, DMASYNC is 0
DMREADY is High
Asynchronous Arbitrate/Xmit
(DMDONE is low)
Arbitrate for Asynchronous Transmit
and Send Asynchronous Packet
Wait for Acknowledge
Ack Complete received
Data Block Done
(DMDONE is low)
End of All Packets
For This Data Block
Yes
Yes
No
Yes
No
No
Yes
DM Disabled
Re-enable via
Software
NOTE: DMEN and DMASYNC are configuration register bits, DMREADY is an input terminal, and DMDONE is an output
terminal.
Figure 5
–
4. Asychronous DM Flow Control (TSB12LV32 Transmit)
The DM Interfaces to the configuration register (CFR), the link core (Link), and the external data mover
interface (DMI).
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