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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 72/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
16
5.2.7
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations is performed:
Asynchronous Packet Receive With Headers and Trailer
Step 1:
The packet router control logic will route the packet to the data mover. At the same time
DMDONE will be asserted high for one DMCLK cycle.
Step 2:
This is followed by DMRW asserted high as the packet comes through. PKTFLAG is only
asserted high when the header quadlets are being received.
Step 3:
After all the data payload has been received on the DMD[0:15] lines, PKTFLAG will be
asserted high again as the trailer quadlet is being received. Once the entire packet is
received, the DMRW line will be asserted low.
Figure 5
–
25 and Figure 5
–
26 show the timing diagram for this mode for the quadlet receive and the block
receive cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5
–
26
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
–
25. Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
Figure 5
–
26. Asynchronous Block Receive With Headers and Trailer at 400 Mbps
5.2.8
In this mode, when the link receives an isochronous packet that is addressed to it, the following sequence
of operations are performed:
Asynchronous Packet Receive Without Headers and Trailer
Step 1:
The packet router control logic will route the packet to the data mover. After the headers
are sent through, DMDONE will be asserted high for one DMCLK cycle.
Step 2:
DMRW is then asserted high as the data payload comes through.
Step 3:
After all data has been received on the DMD[0:15] lines, DMRW will be asserted low and
the trailer quadlet will then come out on the DMD[0:15] lines.
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