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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 70/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
14
Figure 5
–
19 shows the timing diagram at 200 Mbps when the received packet contains only one quadlet
of payload.
Packet payload
0000
DMCLK
DMRW
DMD[0:15]
PKTFLAG
DMDONE
DMPRE
0000
Trailer quadlet
Header quadlet
Figure 5
–
19. Isochronous Receive With Header and Trailer at 200 Mbps
5.2.5
Asynchronous Packet Transmit With Automatic Header Insertion
Upon receiving a high on DMREADY, the following sequence of operations are performed:
Step 1:
DMDONE will be asserted low (deactivated) at the next DMCLK cycle.
Step 2:
The data mover will take the headers that have been loaded into the header0
–
header3
registers and request the link core to transmit the data onto the 1394 bus.
Step 3:
The link core will fetch the headers from the header0
–
header3 registers.
Step 4:
DMPRE will pulse for one DMCLK cycle before the first data quadlet is sent.
Step 5:
The data mover will then begin to fetch the data payload by asserting DMRW high.
Step 6:
When the link core has fetched the last data quadlet, the data mover waits until the
destination node returns an
ack_complete
immediate response. If an
ack_complete
is not
received, the data mover will assert DMERROR high and become disabled.
Figure 5
–
20 and Figure 5
–
21 show the timing diagram for this mode for the quadlet transmit and the block
transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5
–
20.
Figure 5
–
22 shows the block transmit case at 400 Mbps.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
20. Asynchronous Quadlet Transmit With Automatic Header Insertion
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
21. Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps
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