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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 71/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
15
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Figure 5
–
22. Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps
5.2.6
Asynchronous Packet Transmit Without Automatic Header Insertion
Upon receiving a high on DMREADY, the following sequence of operations are performed:
Step 1:
DMDONE will be asserted low (deactivated) at the next DMCLK cycle.
Step 2:
DMPRE will pulse for one DMCLK cycle before the header quadlets are sent.
Step 3:
The data mover will fetch the headers by asserting DMRW high.
Step 4:
The data mover will then load the headers into the header0
–
header3 registers and request
the data to be transmitted out on the 1394 bus by the link core.
Step 5:
The link will fetch the headers.
Step 6:
DMPRE will pulse for one DMCLK cycle before the first data quadlet is sent.
Step 7:
The data mover will then begin to fetch the data payload by asserting DMRW high.
Step 8:
When the link core has fetched the last data quadlet, the data mover waits until the
destination node returns an
ack_complete
immediate response. If an
ack_complete
is not
received, the data mover will assert DMERROR high and become disabled.
Figure 5
–
23 and Figure 5
–
24 show the timing diagram for this mode for the quadlet transmit and the block
transmit cases, respectively. For simplicity, a data block size of three quadlets was selected in Figure 5
–
24.
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Header Quadlets
Data Quadlet
Figure 5
–
23. Asynchronous Quadlet Transmit Without Automatic Header Insertion at 400 Mbps
DMCLK
DMRW
DMD[0:15]
DMREADY
DMPRE
DMDONE
Header Quadlets
Data Quadlets
Figure 5
–
24. Asynchronous Block Transmit Without Automatic Header Insertion at 400 Mbps
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