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參數(shù)資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數(shù)： | 66/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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5
–
10
5.1.4.2
Asynchronous Packet Transmit Without Automatic Header Insertion
In this mode, the packet headers and data information are loaded through the data mover port. This mode
is sometimes called asynchronous packet transmit with manual header insertion. This is because the
header quadlets are not preloaded into the header registers via the microcontroller interface. Instead, they
are inserted
manually
into the data stream at the same time as the rest of the packet. The following steps
further illustrate the process:
Step 1:
Asynchronous header quadlets (3 quadlets in quadlet receive mode and 4 quadlets in block
receive mode) are fetched into the header registers through the data mover port.
Step 2:
The header quadlets are then forwarded to the transmitter of the link core.
Step 3:
Packet data (payload only) is transmitted through the data mover directly to the transmitter
of the link core.
Step 4:
Asynchronous packet is sent to the 1394 bus through the Phy.
CFR REGISTER
Step 4
Header0 Register at 38h
LINK CORE
Transmitter
Receiver
Quadlet#0
Packet sent
to 1394 bus
through the
Phy
Header1 Register at 3Ch
Quadlet#1
Header2 Register at 40h
Quadlet#2
Header3 Register at 42h
Quadlet#3
Data
Mover
Port
Step 3 (packet data)
Step 2
Step 3
(package data)
Step 1
(headers fetched)
Step 1
(Headers supplied)
Figure 5
–
12. Asynchronous Transmit Without Auto Header Insertion
5.2
Data Mover Modes of Operation
The data mover (DM) port in the GP2Lynx is meant to handle an external memory interface of large data
packets. The port can be configured to either transmit or receive data packets. The data can be either
asynchronous or isochronous packets. All traffic through the data mover is synchronous to the rising edge
of DMCLK. DMCLK is an output signal at 25 MHz.
The data mover operates by setting the DM control registers. If the DM is configured for transmit mode, it
waits for DMREADY to be asserted before it can drive DMDONE low and fetch the entire block of data one
packet at a time. Upon transmitting the last packet in the block, the DM will drive DMDONE high for a
minimum of one DMCLK cycle (~ 40 ns). The next DMCLK cycle in which DMDONE finds DMREADY high,
the process will be restarted.
The data mover has eight modes of operation which are specified by the DMASYNC, DMHDR, and DMRX
bits in the DM control register at 04h. Table 5
–
1 shows all the DM modes of operation.
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