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參數資料
| 型號： | TSB12LV22PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER |
| 中文描述： | OHCI的山貓基于PCI的1394主控制器 |
| 文件頁數： | 94/106頁 |
| 文件大小： | 605K |
| 代理商： | TSB12LV22PZP |
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8
–
1
8 TSB12LV32/Phy Interface
This section provides an overview of the digital interface between a TSB12LV32 and a physical layer device
(Phy). The information that follows can be used as a guide through the process of connecting the
TSB12LV32 to a 1394 Phy. The part numbers referenced, the TSB41LV03A and the TSB12LV32, represent
the Texas Instruments implementation of the Phy (TSB41LV03A) and link (TSB12LV32) layers of the IEEE
1394-1995 and P1394a standards.
The specific details of how the TSB41LV03A device operates are not discussed in this document. Only those
parts that relate to the TSB12LV32 Phy interface are mentioned.
8.1
Principles of Operation
The TSB12LV32 is designed to operate with a Texas Instruments physical-layer device. The following
paragraphs describe the operation of the Phy-LLC interface assuming a TSB41LV03A Phy. The
TSB41LV03A is an IEEE 1394a three port cable transceiver/arbiter Phy capable of 400 Mbits/s speeds.
The interface to the Phy consists of the SCLK, CTL0
–
CTL1, D0
–
D7, LREQ, LPS, LINKON, and DIRECT
terminals on the TSB12LV32, as shown in Figure 8
–
1. Refer to Texas Instruments
Application Report
SLLA044
for a detailed description of the electrical interface between the TSB12LV32 and TSB41LV03.
TSB12LV32
Link-Layer
Controller
DIRECT
LINKON
LPS
SCLK
LREQ
D0
–
D7
CTL0
–
CTL1
TSB41LV03A
Physical-Layer
Device
ISO
C/LKON
LPS
SYSCLK
LREQ
D0
–
D7
CTL0
–
CTL1
ISO
DIRECT
Phy/LLC Interface
Figure 8
–
1. Phy-LLC Interface
The SYSCLK from the Phy terminal provides a 49.152 MHz interface clock. All control and data signals are
synchronized to, and sampled on, the rising edge of SYSCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and
data between the TSB41LV03A and TSB12LV32.
The D0
–
D7 terminals form a bidirectional data bus, which is used to transfer status information, control
information, or packet data between the devices. The TSB41LV03A supports S100, S200, and S400 data
transfers over the D0
–
D7 data bus. In S100 operation only the D0 and D1 terminals are used; in S200
operation only the D0
–
D3 terminals are used; and in S400 operation all D0
–
D7 terminals are used for data
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