- 您現在的位置：買賣IC網 > PDF目錄382720 > UCB1500 (NXP SEMICONDUCTORS) PCI to AC97 bridge/host controller PDF資料下載
參數資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數： | 23/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁
Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
23 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.1.7
[0016]: Transmit DMA #1 FIFO count register
8.1.8
[0017]: Transmit DMA #1 command register
Table 28: Transmit DMA #1 FIFO count register bit description
Bit
Description
15(r)
Open PCI Master Cycle
(for internal use only)
This bit is set if there is an outstanding PCI master cycle as a result of PCI retry
termination by the target. Software should wait for this bit to be cleared when
initiating another DMA transfer right after an aborted DMA transfer.
14
DTP Invalid Bit Mask
If this bit is set to ‘1’, the transmit DMA engine will transmit data from the current
descriptor fetched even if the invalid bit set.
13-7
Reserved.
6-0(r)
Transmit DMA #1 FIFO count
(for internal use only)
Number of bytes to be transmitted that is still in the internal 64-byte FIFO.
Table 29: Transmit DMA #1 Command Register bit description
Bit
Description
15-14
Threshold level
Specifies the level at which data is transferred from the memory to the 64-byte
transmit FIFO. The recommended setting for this register is 32 bytes threshold.
00 = 16 bytes, data will be transferred from memory as soon as there is at
least 16 bytes of free space in the transmit FIFO.
01 = 32 bytes
10 = 48 bytes
11 = 60 bytes
Reserved.
Transmit DMA #1 Abort status
This read-only bit is set if the transmit channel has been aborted as a result of a
PCI, D-channel contention or a software abort. The condition is cleared by
writing a ‘1’ to the transmit DMA clear abort bit, bit 5 of this register.
Transmit DMA #1 DT full
This read only bit is set whenever all the transmit descriptors for DMA #1 have
been used, and the transmit DMA is done. If descriptor table is setup as a
circular queue, this bit does not become set. Writing a 1 to this register clears
this status bit.
Reserved.
Transmit-DMA #1 active status
If set, DT of transmit DMA #1 is currently transmitting data.
Transmit DMA #1 enable
Must be set to 1.
Reserved.
Clear Abort
Set this bit to 1 to clear abort status initiated by setting the transmit abort bit. This
bit clears the PCI abort and transmit abort condition. This is a write only bit and it
automatically goes back to 0 after one clock.
13
12(r)
11(r)
10-9
8(r)
7
6
5(w)
相關PDF資料 |
PDF描述 |
|---|---|
| UCC1913D | Very low drop voltage regulators with inhibit |
| UCC1913DTR | Analog IC |
| UCC1913J | Very low drop voltage regulators with inhibit |
| UCC1913N | Very low drop voltage regulators with inhibit |
| UCC1926DS | Very low drop voltage regulators with inhibit |
相關代理商/技術參數 |
參數描述 |
|---|---|
| UCB1510 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:AC97 digital modem codec |
| UCB15-101T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
| UCB1510DB | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:AC97 digital modem codec |
| UCB15-121T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
| UCB15-600T-RC | 制造商:ALLIED 制造商全稱:Allied Components International 功能描述:Ultra Current Beads |
發布緊急采購，3分鐘左右您將得到回復。