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參數資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數： | 37/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
37 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.6.10
[00c9]: AC97 command/GPIO control and status register
Table 55: AC97 command/GPIO control and status register bit description
Bit
Description
15-10
Reserved.
9
Valid GPIO data
Reads to this register will return a “1” if there is valid read data from the codec
connected to AC97 channel #0 in register CDh. Writing a “1” to this bit will clear
the status.
8
AC97 command GPIO enable
Writing a 1 to this bit issues GPIO data to slot 12. Data is specified in register
CDh. When enabled, specified value will be transmitted repeatedly during slot 12
timeslot. Writing a “0” to this bit will disable GPIO transmit (slot12 = ‘h00000,
tag big = invalid).
7
Slotreq #1 enable
If “1”, UCB1500 will monitor the slotreq bits from codec enabled on DMA
channel #1. Used for 'On demand” sample transport scheme.
6
Slotreq #0 enable
If “1”, UCB1500 will monitor the slotreq bits from codec enabled on DMA
channel #0. Used for 'On demand” sample transport scheme.
5-3
Power-up Sync counter
Register counts the number of audio frame times since AC97 Bit Clock was
restarted. This 3-bit counter counts up to 4, then remains 4 until the next time the
AC97 power down occurs.
0000 = 0 SYNC frame periods have occurred after power-up.
0001 = 1 SYNC frame periods have occurred after power-up.
0010 = 2 SYNC frame periods have occurred after power-up.
0011 = 3 SYNC frame periods have occurred after power-up.
0100 = 4 SYNC frame periods have occurred after power-up.
0101-1111 = Reserved.
BITCLK status
This bit is set if the BITCLK is detected idle for PCLK
×
48 period, or
approximately 1.4
μ
s. After PCLK
×
66 time period has passed, or about 2
μ
s,
the SDATAOUT and SYNC signals are forced to zero.
Warm AC97 Reset
Writing a “1” to this register will cause UCB1500 to generate a Warm AC97 reset
by driving SYNC HIGH for a minimum of 1
μ
s. Reads to this bit will return a “1”
while power-up is in progress. Warm AC97 reset will only occur if BITCLK is
inactive for at least 1 audio frame. Writes to this bit is ignored if BITCLK is active.
Reserved.
2
1
0
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