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參數資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數： | 42/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
42 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.7 Status port registers
The following registers are used for event notification. If the corresponding interrupt is
enabled, and interrupt will be generated when an event occurs. For each event, write
‘1’ to the corresponding bit to clear it.
8.7.1
[Base address + 4]: Status port 1
8.7.2
[Base address + 8]: Reserved
8.7.3
[Base address + c]: Status port 2 (AC97 interrupt status)
Table 65: Status port 1 register bit description
Bit
Description
31-28(r)
Reserved.
27(r)
Transmit DMA #0 error
26(r)
Transmit DMA #1 error
25-24
Reserved.
23(r)
Transmit DMA #0 DT done/Hold
22(r)
Transmit DMA #1 DT done/Hold
21-20
Reserved.
19(r)
Transmit DMA #0 done
18(r)
Transmit DMA #1 done
17-16
Reserved.
15(r)
Counter #1 interrupt
14(r)
Counter #0 interrupt
13-12
Reserved.
11(r)
Receive DMA #0 error
10(r)
Receive DMA #1 error
9-8
Reserved.
7(r)
Receive DMA #0 DT done/Hold
6(r)
Receive DMA #1 DT done/Hold
5-4
Reserved.
3(r)
Receive DMA #0 done
2(r)
Receive DMA #1 done
1-0
Reserved.
Table 66: Status port 2 (AC97 interrupt status) register bit description
Bit
Description
31-25
Reserved.
24(r)
AC97 GPIO_INT occurred
23-0
Reserved.
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