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參數(shù)資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 40/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
40 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
8.6.20
[d8]: AC97 wake-up enable register
This register is powered by V
aux
and sticky.
8.6.21
[d9]: AC97 wake-up status register
This register is powered by V
aux
and sticky.
Table 61: AC97 wake-up enable register bit description
Bit
Description
15-12
Reserved.
11-1
Reserved.
7
AC97 Channel #0 wake-up enable
Write “1” to enable wake-up on AC97 SDATAIN[0] active on channel #0. If “1”, a
LOW-to-HIGH transition of SDATAIN[0] will:
set
AC97 Channel #0 wake-up status
to “1”.
set
PME Status
of Function 0 PCI configuration register 84h to “1”.
Subsequent clearing of Function 0
PME Status
is independent of clearing of
AC97 Channel #0 wake-up status.
AC97 Channel #1 wake-up enable
Write “1” to enable wake-up on AC97 SDATAIN[1] active on channel #1. If “1”, a
LOW-to-HIGH transition of SDATAIN[1] will:
6
set
AC97 Channel #1 wake-up status
to “1”.
set
PME Status
of Function 1 PCI configuration register 84h to “1”.
Subsequent clearing of Function 1
PME Status
is independent of clearing of
AC97 Channel #1 wake-up status.
Reserved.
5-0
Table 62: AC97 wake-up status register bit description
Bit
Description
15-12
Reserved.
11-8
Reserved.
7
AC97 Channel #0 wake-up status
1 = AC97 channel #0 wake-up event occurred. Write “1” to clear. This status bit is
set if a LOW-to-HIGH transition occurs in SDATAIN[0] and
AC97 Channel #0
wake-up enable
of register d8h is set.
6
AC97 Channel #1 wake-up status
1 = AC97 channel #1 wake-up event occurred. Write “1” to clear. This status bit is
set if a LOW-to-HIGH transition occurs in SDATAIN[1] and
AC97 Channel #1
wake-up enable
of register d8h is set.
5-0
Reserved.
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