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參數資料
| 型號： | UCB1500 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI to AC97 bridge/host controller |
| 中文描述： | PCI BUS CONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數： | 43/58頁 |
| 文件大小： | 1001K |
| 代理商： | UCB1500 |
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Objective specification
Rev. 01 — 4 February 2000
43 of 58
9397 750 06854
Philips Electronics N.V. 2000. All rights reserved.
9.
DMA engine application notes
All DMA transfers use Descriptor Tables (DT). The DT must be contiguous in the Host
memory, and each DMA channel must have its own DT set up as one buffer. For
transmission, each DT must have not empty DT entries, and the last entry of a DT
must point to valid data, or to a linked descriptor table. Each DT entry is 8 bytes in
size. It contains the base address, byte count and command/status bits as illustrated
in
Figure 4
.
Each DMA channel has a DTP (Descriptor Table Pointer), which points to entries in
the descriptor tables. When the last entry in the descriptor table is reached, and the
corresponding buffer is completely utilized, the DMA controller can jump to a new
descriptor table, if necessary, as specified by the link bit of the last entry. The entire
process is repeated for the remainder of the transfer session.
Note:
1. DT must be quad-word aligned. There are no restrictions to the size of the DT. No
empty DT entries are allowed. The DT has to be in the continuous physical
memory space up to 4 GigaBytes.
2. The data buffer area pointed by each DT entry must not exceed 64K
1 in size.
The data address must be double-word aligned as the UCB1500 fetches 4 bytes
at a time.
Fig 4.
Descriptor Table entry format
31
0
23
15
BYTE
0
4
Data area BASEADDR in physical memory
CMD/STT
COUNT
SC00209
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