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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 11/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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11
A
I
D
6. INTERFACE DESCRIPTION
MII Interface (MII)
The ACD82124 communicates with the external 10/
100 Ethernet transceivers through standard MII inter-
face. The signals of MII interface are described in
table-6.1:
For MII interface, signal PxRXDV, PxRXER and
PxRXD0 through PxRXD3 are sampled by the rising
edge of PxRXCLK. Signal PxTXEN, and PxTXD0
through PxTXD3 are clocked out by the falling edge of
PxTXCLK. The detailed timing requirement is described
in the chapter of “Timing Description”
Ports 0,1, 2, 3, 4, 5, 6, 7, 22 and 23 can be config-
ured as reversed MII ports (Register 28 the Reversed
MII Enable register). These ports, when configured as
“normal” MII, have the same characteristics as all other
MII ports. However, when configured as reversed MII
interface, they will behave logically like a PHY device,
and can interface directly with a MAC device. The
signal of reversed MII interface are described by table-
6.2:
Note: * Collision Indicationfor half-duplex mode.
Not-Ready (output)for full duplex mode.
For reversed MII interface, signal PxRXDVR, and
PxRXD0R through PxRXD3R are clocked out by the
falling edge of PxRXCLKR. Signal PxTXENR, and
PxTXD0R through PxTXD3R can be sampled by the
falling edge or rising edge of PxTXCLKR, depends on
the setting of bit 9 of Register 16 The timing behavior
is described in the chapter of “Timing Description.“
PHY Management Interface
All control and status registers of the PHY devices are
accessible through the PHY management interface.
The interface consists of two signals: MDC and MDIO,
which are described in Table-6.3
Frames transmitted on MDIO has the following format
(Table-6.4):
Table-6.1: MII Interface Signals
Name
Type
PxCRS
PxRXDV
PxRXCLK
PxRXERR
PxRXD0
PxRXD1
PxRXD2
PxRXD3
PxCOL
PxTXEN
O
PxTXCLK
PxTXD0
O
PxTXD1
O
PxTXD2
O
PxTXD3
O
Description
I
I
I
I
I
I
I
I
I
Carrier sense
Receive data valid
Receive clock (25/2.5 MHz)
Receive error
Receive data bit 0
Receive data bit 1
Receive data bit 2
Receive data bit 3
Collision indication
Transmit data valid
Transmit clock (25/2.5 MHz)
Transmit data bit 0
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
I
Table-6.2: Reversed MII Interface Signals
Name
Type
PxCRSR
O
PxRXDVR
I
PxRXCLKR
O
PxRXERR
I
PxRXD0R
I
PxRXD1R
I
PxRXD2R
I
PxRXD3R
I
Description
Carrier sense
Transmit data valid
Transmit clock (25/2.5 MHz)
Not-Ready (Input)
Transmit data bit 0
Transmit data bit 1
Transmit data bit 2
Transmit data bit 3
Collision Indication/
Not-Ready (Output)
Receive data valid
Receive clock (25/2.5 MHz)
Receive data bit 0
Receive data bit 1
Receive data bit 2
Receive data bit 3
PxCOLR
O
PxTXENR
PxTXCLKR
PxTXD0R
PxTXD1R
PxTXD2R
PxTXD3R
O
O
O
O
O
O
Table-6.3: PHY Management Interface Signals
Name
Type
MDC
O
PHY management clock (1.25MHz)
MDIO
I/O
PHY management data
Description
Table-6.4: MDIO Format
Operation
Write
Read
PRE
1…1
1…1
ST
01
01
OP
01
10
PHY-ID
aaaaa
aaaaa
REG-AD
rrrrr
rrrrr
TA
10
Z0
DATA
d…d
d…d
IDLE
Z
Z
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