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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 42/48頁 |
| 文件大?。?/td> | 411K |
| 代理商： | ADC82124 |
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3. FUNCTIONAL DESCRIPTION
The ARL provides Address Resolution service for
ACD’s switch controllers. Figure 2is a block diagram
of the ARL.
Traffic Snooping
All Ethernet frames received by ACD’s switch control-
ler have to be stored into memory buffer. As the frame
data are written into memory, the status of the data
shown on the data bus are displayed by ACD’s switch
controller through a state bus. The ARL’s Switch Con-
troller Interface contains the signals of the data bus
and the state bus. By snooping the data bus and the
state bus of ACD’s switch controller, the ARL can de-
tect the occurrence of any destination MAC address
and source MAC address embedded inside each frame.
Address Learning
Each source address caught from the data bus, to-
gether with the ID of the ingress port, is passed to the
Address Learning Engine of the ARL. The Address
Learning Engine will first determine whether the frame
is a valid frame. For a valid frame, it will first try to find
the source address from the current address table. If
that address doesn’t exist, or if it does exist but the
port ID associated with the MAC address is not the
ingress port, the address will be learned into the ad-
dress table. After an address is learned by the ad-
dress learning engine, the CPU will be notified to read
this newly learned address so that it can add it into the
CPU’s address table.
Address Aging
After each source address is learned into the address
table, it has to be refreshed at least once within each
address aging period. Refresh means it is caught again
from the switch interface. If it has not occurred for a
pre-set aging period, the address aging engine will
remove the address from the address table. After an
address is removed by the address aging engine, the
CPU will be notified through interrupt request that it
needs to read this aged out address so that it can
remove this address from the CPU’s address table.
Address Lookup
Each destination address is passed to the Address
Lookup Engine of the ARL. The Address Lookup En-
gine checks if the destination address matches with
any existing address in the address table. If it does,
the ARL returns the associated Port ID to ACD’s switch
controller through the output data bus. Otherwise, a
no match result is passed to ACD’s switch controller
through the output data bus.
CPU Interface
The CPU can access the registers of the ARL by send-
ing commands to the UART data input line. Each com-
mand is consisted by action (read or write), register
type, register index, and data. Each result of com-
mand execution is returned to the CPU through the
UART data output line.
CPU Interface Registers
The ARL provides a bunch of registers for the control
CPU. Through the registers, the CPU can read all ad-
dress entries of the address table, delete particular
addresses from the table, add particular addresses
into the table, secure an address from being changed,
set filtering on some addresses, change the hashing
algorithm etc. Through a proper interrupt request sig-
nal, the CPU can be notified whenever it needs to
retrieve data for a newly-learned address or an aged-
out address so that the CPU can build an exact same
address table learned by the ARL.
CPU Interface Engine
The command sent by the control CPU is executed by
the CPU Interface Engine. For example, the CPU may
send a command to learn the first newly-learned ad-
dress. The CPU Interface Engine is responsible to
find the newly-learned address from the address table,
and passes it to CPU. The CPU may request to learn
next newly-learned address. Then, it is again the re-
sponsibility of the CPU Interface Engine to search for
next newly-learned address from the address table.
Address Table
The address table can hold up to 2,048 MAC ad-
dresses, together with the associated port ID, security
flag, filtering flag, new flag, aging information etc. The
address table resides in the embedded SRAM inside
the ARL.
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