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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 23/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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23
A
I
D
Table-7.25: POSCFG Register
Bit
3:0
8 timing adjustment levels for SRAM Read data latching:
0000 - no delay
0001 - level 1 delay
0011 - level 2 delay
0101 - level 3 delay
0111 - level 4 delay
1001 - level 5 delay
1011 - level 6 delay
1101 - level 7 delay
1111 - level 8 delay
4
0 - Absolute address mode: 1 row of 512K words, nCS2=ADDR17, nCS3=ADDR18
1 - Chip-Select address mode: 4 rows of 128K words, nCS[3:0] to select 4 rows of memory
6:5
SRAM size selection:
00 - 64K words
01 - 128K words
10 - 256k words
11 - 512K words
7
0 - Long Event defined as frame longer than 1518 byte.
1 - Long Event defined as frame longer than 1530 byte.
8
0 - Frames with unknown DA forwarded to the dumping port.
1 - Frames with unknown DA forwarded to all ports.
9
0 - Internal ARL selected (2K MAC address entry).
1 - External ARL selected (11K MAC address entry).
10
0 - PHY IDs start from 1, range from 1 to 24.
1 - PHY IDs start from 4, range from 4 to 27.
11
0 - Re-transmit after excessive collision.
1 - Drop after excessive collision.
12
0 - Automatic PHY Management enabled
1 - Automatic PHY Management disabled: the control CPU need to update the SPEED, LINK, DPLX and
nPAUSE registers
13
0 - Rising edge of RxClk triggering for regular MII ports
0 - Falling edge of RxClk triggering for regular MII ports
14
0 - Sysem errors will trigger software reset
1 - Sysem errors will trigger hardware reset
15
0 - System start itself without a control CPU
1 - System start after system-ready bit in register-16 is set by the control CPU
2-bit device ID for UART communication. The device responses only to UART commands with
matching ID
18
0 - Rising edge of ARLCLK to latch ARLDI.
1 - Falling edge of ARLCLK to latch ARLDI.
Description
Default
0000
0
000
0
0
0
0
0
0
0
0
0
17:16
00
0
POSCFG register (register 25)
The POSCFG register specifies a certain configura-
tion setting for the switch system. The default values of
this register can be changed through pull-up/pull-down
of specific pins, as described in the “Configuration
Interface” section of the “Interface Description” chap-
ter. Table-7.25 describes all the bit of this register.
FdEn register (register 26)
FdEn register is used to specify if an even numbered
port has been connected as a full duplex port. The
default value of FdCfg is determined by Pull-High or
Pull-Low status of the hardware pins shown in Table-
26.
DPLX register (register 27)
The DPLX register specifies or indicates the half/full-
duplex mode of each of the 12 even-numbered ports
(port 0, 2, 4, .. 20 and 22). It is read-only, unless bit-
12 of register-25 is set (through POS, to disable auto-
matic PHY management). At read-only mode, it indi-
cates the result achieved by the PHY management. At
write-able mode, the control CPU can assign a half-
duplex or full-duplex mode for each of the 12 even-
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