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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 41/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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A
I
D
1. SUMMARY
The internal Address Resolution Logic (ARL) of ACD’s
switch controllers automatically builds up an address
table and maps up to 2,048 MAC addresses into their
associated port. It can work by itself without any CPU
intervention in an UN-managed system.
For a managed system, the management CPU can
configure the operation mode of the ARL, learn all the
address in the address table, add new address into
the table, control security or filtering feature of each
address entry etc.
The ARL is designed with such a high performance
that it will never slow down the frame switching opera-
tion. It helps the switch controllers to reach wire speed
forwarding rate under any type of traffic load.
The address space can be expanded to 11K entries
by using the external ARL, the ACD80800.
2. FEATURES
Supports up to 2,048 MAC address lookup
Provides UART type of interface for the manage-
ment CPU
Wire speed address lookup time.
Wire speed address learning time.
Address can be automatically learned from switch
without the CPU intervention
Address can be manually added by the CPU
through the CPU interface
Each MAC address can be secured by the CPU
from being changed or aged out
Each MAC address can be marked by the CPU
from receiving any frame
Each newly learned MAC address is notified to
the CPU
Each aged out MAC address is notified to the CPU
Automatic address aging control, with configurable
aging period
CPU Interface
A
R
D
R
C
R
C
R
Switch Interface
Address
Learning
Engine
CPU Interface Engine
Address Table
(2048 Entries)
Figure-1. ARL Block Diagram
Address
Aging
Engine
Address
Lookup
Engine
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