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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 15/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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15
A
I
D
Table-6.11: Configuration Interface
Pin Name
Register #
P7TXD0
P7TXD1
P7TXD2
P7TXD3
P6TXD0
P6TXD1
P6TXD2
P6TXD3
LEDCLK
LEDVLD0
LEDVLD1
nLED3
nLED2
nLED1
nLED0
P5TXD0
P5TXD1
P5TXD2
P5TXD3
P2TxD0
P2TxD1
P2TxD2
P2TxD3
P3TxD0
P3TxD1
P3TxD2
P3TxD3
P4TxD0
P4TxD1
P4TxD2
P4TxD3
P0TXD0
P0TXD1
P0TXD2
P0TXD3
P1TXD0
P1TXD1
P1TXD2
P1TXD3
P23TXD0R
P23TXD1R
P23TXD2R
P23TXD3R
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
0
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
0
1
2
3
Setting
20, inside the
Internal ARL
0
See Appendix-
A1
25
26
30
See Table-
7.25
See Table-
7.30
See Table-
7.26
Configuration Interface
There are 20 pins whose pull-up or pull-down state will
be used as Power-On-Strobing configuration data (Reg-
ister 25, & CFG0 - CFG19) to specify various working
modes of the ACD82124. The CFG pins are shared
with other functional pins of the ACD82124. The pull-
high or pull-low status of the CFG pins are used to
indicate specific configuration settings, described in
Table-6.11 The register description section will pro-
vide more details about the POS Configuration regis-
ter
Other Interface (Table-6.12)
CLK50 should come from a clock oscillator, with 0.01%
(100 ppm) accuracy.
Assertion of the nRESET pin will cause the ACD82124
to go through the power-up initialization process. All
registers are set to their default value after reset.
When the ACD82124 is working properly, it will gener-
ate pulses from the WCHDOG pin continuously. It is
used as a safeguard, so that in case something unex-
pected happens, the external watchdog circuit will re-
set the switch system.
VDD is 3.3V power supply. VSS is power ground.
Table-6.12: Other Interface
Name
CLK50
nRESET
WCHDOG
VDD
VSS
Type
I
I
O
-
-
Description
50 MHz clock input
hardware reset
watch dog life pulse signal
3.3 V power
ground
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