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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 16/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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16
A
I
D
7. REGISTER DESCRIPTION
Registers in the ACD82124 are used to define the op-
eration mode of various function modules of the switch
controller and the peripheral devices. Default values at
power-on are defined by the factory. The manage-
ment CPU (optional) can read the content of all regis-
ters and modify some of the registers to change the
operation mode. Table-7.0 lists all the registers inside
the switch controller.
INTSRC register (register 1)
The INTSRC register indicates the source of the inter-
rupt request. Before the CPU starts to respond to an
interrupt request, it should read this register to find out
the interrupt source. This register is automatically
cleared after each read. Table-7.1 lists all the bits of
this register.
SYSERR register (register 2)
The SYSERR register indicates the presence of sys-
tem errors. It is automatically cleared after each read.
Table-7.2 lists all kind of system error.
Table-7.1: INTSRC Register
Bit
0
System initialization completed
1
System error occurred
2
Port partition occurred
3
ARL Interrupt
4
Reserved
5
Reserved
6
Reserved
7
Reserved
Description
Default
0
0
0
0
0
0
0
0
Table-7.2: SYSERR Register
Bit
0
BIST failure indication
1
2
3
4
5
6
7
8
Description
Default
0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Table-7.0: Register List
Address
0
1
2
3
4
5
6-15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32-63
Name
Type
Size
Depth
Reserved
Description
INTSRC
SYSERR
PAR
PMERR
ACT
R
R
R
R
R
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
1
1
1
1
1
Reserved
Interrupt Source
System Error
Port Partition Indication
PHY Management Error
Port Avtivity
SYSCFG
INTMSK
SPEED
LINK
nFWD
nBP
nPORT
PVID
VPID
POSCFG
nPAUSE
DPLX
RVSMII
nPM
ERRMSK
CLKADJ
PHYREG
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16 Bit
8 Bit
24 Bit
24 Bit
24 Bit
24 Bit
24 Bit
4 Bit
5 Bit
19 Bit
24 Bit
24 Bit
5 Bit
24 Bit
8 Bit
4 Bit
16 Bit
1
1
1
1
1
1
1
24
4
1
1
1
1
1
1
1
24
System Configuration
Interrupt Mask
Port Speed
Port Link
Port Forward Disable
Port Back Pressure Disable
Port Disable
Port VLAN ID
VLAN Dumping Port
Power-On-Strobe Configuration
Port Pause Frame Disable
Port Duplex Mode
Reversed MII Selection
Port PHY Management Disable
Error Mask
ARL Clock Delay Adjustment
Registers in PHY device, (REG# - 32)
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