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參數資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網開關控制器 |
| 文件頁數： | 5/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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5
A
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5. FUNCTIONAL DESCRIPTION
The MAC controller performs transmit, receive, and
defer functions, in accordance to IEEE 802.3 and
802.3u standard specification. The MAC logic also
handles frame detection, frame generation, error de-
tection, error handling, status indication and flow con-
trol functions.
Frame Format
The ACD82124 assumes that the received data packet
will have the following format:
Where,
Preamble is a repetitive pattern of ‘1010….’ of
any length with nibble alignment.
SFD(Start Frame Delimiter) is defined as an oc-
tet pattern of 10101011.
DA(Destination Address) is a 48-bit field that speci-
fies the MAC address of the destined DTE. If the
first bit of DA is 1, the ACD82124 will treat the
frame as a broadcast/multicast frame and will for-
ward the frame to all ports within the source port’s
VLAN except the source port itself or BPDU ad-
dress.
SA(Source Address) is a 48-bit field that con-
tains the MAC address of the source DTE that is
transmitting the frame to the ACD82124. After a
frame is received with no error, the SA is learned
as the port’s MAC address.
Type/Lenfield is a 2-byte field that specifies the
type (DIX Ethernet frame) or length (IEEE 802.3
frame) of the frame. The ACD82124 does not pro-
cess this information.
Datais the encapsulated information within the
Ethernet Packet. The ACD82124 does not pro-
cess any of the data information in this field.
FCS(Frame Check Sequence) is a 32-bit field of
a CRC (Cyclic Redundancy Check) value based
on the destination address, the source address,
the type/length and the data field. The ACD82124
will verify the FCS field for each frame. The pro-
cedure of computing FCS is described in section
of “FCS Calculation.”
Start of Frame Detection
When a port’s MAC is idle, assertion of the RXDV in
the MII interface will cause the port to go into the re-
ceive state. The MII presents the received data in 4-bit
nibbles that are synchronous to the receive clock
(25Mhz or 2.5MHz). The ACD82124 will convert this
data into a serial bit stream, and attempt to detect the
occurrence of the SFD (10101011) pattern. All data
prior to the detection of SFD are discarded. Once SFD
is detected, the following frame data are forwarded
and stored in the buffer of the switch.
Frame Reception
Under normal operating conditions, the ACD82124
expects a received frame to have a minimum inter frame
gap (IFG). The minimum IFG required by the device is
80 BT (Bit Time).
In the event the ACD82124 receives a packet with IFG
less than 80BT, the ACD82124 does not guarantee to
be able to receive the frame. The packet will be dropped
if the ACD82124 cannot receive the frame.
The device will check all received frames for errors
such as symbol error, FCS error, short event, runt,
long event, jabber etc. Frames with any kind of error
will not be forwarded to any port.
Preamble Bit Processing
The preamble bit in the header of each frame will be
used to synchronize the MAC logic with the incoming
bit stream. The minimum length of the preamble is 0
bits and there is no limitation on the maximum length of
preamble. After the receive data valid signal RXDV is
asserted by the external PHY device, the port will wait
for the occurrence of the SFD pattern (10101011) and
then start a frame receiving process.
Source Address and Destination Address
After a frame is received by the ACD82124, the em-
bedded destination address and source address are
retrieved. The destination address is passed to the
lookup table to find the destination port. The source
address is automatically stored into the address lookup
table. For applications that use an external ARL, the
ACD82124 will disable the internal lookup table and
pass the DA and SA to the external ARL for address
lookup and learning.
Preamble SFD DA SA Type/Len Data FCS
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