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參數(shù)資料
| 型號： | ADC82124 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 24 Ports 10/100 Fast Ethernet Switch Controller |
| 中文描述： | 24端口10/100快速以太網(wǎng)開關(guān)控制器 |
| 文件頁數(shù)： | 9/48頁 |
| 文件大小： | 411K |
| 代理商： | ADC82124 |
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and are lined up in the transmission queues of the
corresponding destination port. The order of all frames,
unicast or broadcast, is strictly enforced by the
ACD82124. The ACD82124 is designed with a non-
blocking switching architecture. It is capable of achiev-
ing wire-speed frame forwarding rate and handling
maximum traffic load.
MII Interface
The MAC of each port of the ACD82124 interfaces
with the port’s PHY device through the standard MII
interface. For reception, the received data (RXD) can
be sampled by the rising edge (default) or the falling
edge of the receive clock (RXCLK). Assertion of the
receive data valid (RXDV) signal will cause the MAC to
look for start of Frame Delimiter (SFD). For transmis-
sion, the transmit data enable (TXEN) signal is as-
serted when the first preamble nibble is sent on the
transmit data (TXD) lines. The transmit data are clocked
out by the falling edge of the transmit clock (TXCLK).
The ACD82124 supports PHY device management
through the serial MDIO and MDC signal lines. The
ACD82124 can continuously poll the status of the PHY
devices through the serial management interface, with-
out CPU intervention. The ACD82124 will also config-
ures the PHY capability field to ensure proper opera-
tion of the link. The ACD82124 also enables the CPU
to access any registers in the PHY devices through
the CPU interface.
Reversed MII Interface
Ten ports of the ACD82124 can be configured as re-
versed MII interface. Reversed MII behaves as a PHY
MII, that the TXCLK, COL, RXD<3:0>, RXCLK, RXDV,
CRS signals (names specified by IEEE 802.3u) be-
come output signals of the ACD82124, and the TXER,
TXD<3:0>, TXEN, RXER, signals (names specified by
IEEE 802.3u) become input signals of the ACD82124.
Reversed MII interface enables an external MAC de-
vice to be connected directly with the ACD82124.
ASRAM Interface
The ACD82124 requires the use of asynchronous
SRAM as a memory buffer. Each read or write cycle
takes up to 20 ns. An ASRAM chip with access speed
at 12 ns or faster should be used. The ASRAM inter-
face contains a 52-bit data bus, a 17-bit address bus
and 4 chip-select signals.
CPU Interface
The ACD82124 does not require a microprocessor for
operation. Initialization and most configurations can
be done with the use of external hardware pins. How-
ever, the ACD82124 provides a CPU interface for a
microprocessor to access some of its control regis-
ters and status registers. The microprocessor can send
a read command to retrieve the status of the switch, or
send a write command to configure the switch through
a serial interface. This interface is a commonly used
UART type interface. The CPU interface can also be
used to access the registers inside each PHY device
connected with the ACD82124.
ARL Interface
The ACD82124 has a built-in ARL that can store up to
2,000 MAC addresses. It is actually a subset of the full
ACD80800 ARL IC. For detailed description, please
refer to the ACD80800 Data Sheet. The UARTID for
this built-in ARL is shared with the ACD82124 (CFG16
& 17).
The ACD82124 also provides an ARL interface (Table
12: CFG9)for supporting additional MAC addresses.
Through the ARL interface, the external ARL
(ACD80800) device can tap the value of DA out from
the data bus in the ASRAM interface, and execute a
lookup process to map the value of DA into a port
number. The external ARL device also learns the SA
values embedded in the received frames via the ARL
interface. The value of SA is used to build up the ad-
dress lookup table.
MIB Interface
Traffic activities on all ports of the ACD82124 can be
monitored through the MIB interface. Through the MIB
interface, a MIB device can view what the source port
is receiving, or what the destination port is transmit-
ting. Therefore, the MIB device can maintain a record
of traffic statistics for each port to support network
management. Since all received data are stored into
the memory buffer, and all transmitted data are re-
trieved from the memory buffer, the data of the activi-
ties can also be captured from the data bus of ASRAM
interface. The status of each data transaction between
the ACD82124 and the ASRAM is displayed by some
dedicated status signal pins of the ACD82124.
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