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| 型號： | ADSP-21161NCCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數(shù)： | 14/60頁 |
| 文件大小： | 1019K |
| 代理商： | ADSP-21161NCCA-100 |
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ADSP-21161N
–14–
REV. A
HBG
I/O
Host Bus Grant.
Acknowledges an
HBR
bus request, indicating that the host processor
may take control of the external bus.
HBG
is asserted (held low) by the ADSP-21161N until
HBR
is released. In a multiprocessing system,
HBG
is output by the ADSP-21161N bus
master and is monitored by all others.
After
HBR
is asserted, and before
HBG
is given,
HBG
will float for 1 t
CK
(1 CLKIN cycle).
To avoid erroneous grants,
HBG
should be pulled up with a 20k
to 50k
external resistor.
Chip Select.
Asserted by host processor to select the ADSP-21161N.
Host Bus Acknowledge
. The ADSP-21161N deasserts REDY (low) to add wait states to
a host access of its IOP registers when
CS
and
HBR
inputs are asserted.
DMA Request 1
(DMA Channel 11). Asserted by external port devices to request DMA
services.
DMAR1
has a 20 k
internal pull-up resistor that is enabled for DSPs with
ID2
–
0=00x.
DMA Request 2
(DMA Channel 12). Asserted by external port devices to request DMA
services.
DMAR2
has a 20 k
internal pull-up resistor that is enabled for DSPs with
ID2
–
0=00x.
DMA Grant 1
(DMA Channel 11). Asserted by ADSP-21161N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
DMAG1
has a 20 k
internal pull-up resistor that is enabled for DSPs with ID2
–
0=00x.
DMA Grant 2
(DMA Channel 12). Asserted by ADSP-21161N to indicate that the
requested DMA starts on the next cycle. Driven by bus master only.
DMAG2
has a 20 k
internal pull-up resistor that is enabled for DSPs with ID2
–
0=00x.
Multiprocessing Bus Requests
. Used by multiprocessing ADSP-21161Ns to arbitrate for
bus mastership. An ADSP-21161N only drives its own
BRx
line (corresponding to the value
of its ID2
–
0 inputs) and monitors all others. In a multiprocessor system with less than six
ADSP-21161Ns, the unused
BRx
pins should be pulled high; the processor's own
BRx
line
must not be pulled high or low because it is an output.
Bus Master Output
. In a multiprocessor system, indicates whether the ADSP-21161N is
current bus master of the shared external bus. The ADSP-21161N drives BMSTR high only
while it is the bus master. In a single-processor system (ID=000), the processor drives this
pin high. This pin is used for debugging purposes.
Multiprocessing ID
. Determines which multiprocessing bus request (
BR6
–
BR1
) is used
by ADSP-21161N. ID=001 corresponds to
BR1
, ID=010 corresponds to
BR2
, and so on.
Use ID=000 or ID=001 in single-processor systems. These lines are a system configuration
selection that should be hardwired or only changed at reset.
Rotating Priority Bus Arbitration Select
. When RPBA is high, rotating priority for
multiprocessor bus arbitration is selected. When RPBA is low, fixed priority is selected. This
signal is a system configuration selection that must be set to the same value on every ADSP-
21161N. If the value of RPBA is changed during system operation, it must be changed in
the same CLKIN cycle on every ADSP-21161N.
Priority Access
. Asserting its
PA
pin enables an ADSP-21161N bus slave to interrupt
background DMA transfers and gain access to the external bus.
PA
is connected to all ADSP-
21161Ns in the system. If access priority is not required in a system, the
PA
pin should be
left unconnected.
PA
has a 20 k
internal pull-up resistor that is enabled for DSPs with
ID2
–
0=00x.
Data Transmit or Receive Channel A
(Serial Ports 0, 1, 2, 3). Each DxA pin has an
internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output
to transmit serial data, or as an input to receive serial data.
Data Transmit or Receive Channel B
(Serial Ports 0, 1, 2, 3). Each DxB pin has an
internal pull-up resistor. Bidirectional data pin. This signal can be configured as an output
to transmit serial data, or as an input to receive serial data.
Transmit/Receive Serial Clock
(Serial Ports 0, 1, 2, 3). Each SCLK pin has an internal
pull-up resistor. This signal can be either internally or externally generated.
CS
REDY
I/A
O (O/D)
DMAR1
I/A
DMAR2
I/A
DMAG1
O/T
DMAG2
O/T
BR6–1
I/O/S
BMSTR
O
ID2
–
0
I
RPBA
I/S
PA
I/O/T
DxA
I/O
DxB
I/O
SCLKx
I/O
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
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