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參數資料
| 型號： | ADSP-21161NCCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數： | 51/60頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | ADSP-21161NCCA-100 |
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–51–
REV. A
ADSP-21161N
Output Drive Currents
Figure 37
shows typical I-V characteristics for the output drivers
of the ADSP-21161N. The curves represent the current drive
capability of the output drivers as a function of output voltage.
Test Conditions
The DSP is tested for output enable, disable, and hold time.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
ENA
is the interval from the
point when a reference signal reaches a high or low voltage level
to the point when the output has reached a specified high or low
trip point, as shown in the Output Enable/Disable diagram
(
Figure 38
). If multiple pins (such as the data bus) are enabled,
the measurement value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driving,
go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by
V is dependent on the capacitive load, C
L
and the
load current, I
L
. This decay time can be approximated by the
following equation:
C
V
--------------------
=
The output disable time t
DIS
is the difference between t
MEASURED
and t
DECAY
as shown in
Figure 38
. The time t
MEASURED
is the
interval from when the reference signal switches to when the
output voltage decays
V from the measured output high or
output low voltage. t
DECAY
is calculated with test loads C
L
and I
L
,
and with
V equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose
V
to be the difference between the ADSP-21161N’s output voltage
and the input threshold for the device requiring the hold time. A
typical
V will be 0.4 V. C
L
is the total bus capacitance (per data
line), and I
L
is the total leakage or three-state current (per data
line). The hold time will be t
DECAY
plus the minimum disable time
(i.e., t
DATRWH
for the write cycle).
Figure 37. Typical Drive Currents
SWEEP (V
DDEXT
) VOLTAGE – V
60
–10
–40
0
3.5
0.5
1.0
1.5
2.0
2.5
3.0
50
0
–20
–30
30
10
40
20
–50
–60
L
D
)
V
DDEXT
= 3.47V, –40°C
V
DDEXT
= 3.3V, +25°C
V
DDEXT
= 3.13V, +105°C
V
DDEXT
= 3.13V, +105°C
V
DDEXT
= 3.47V, –40°C
V
DDEXT
= 3.3V, +25°C
80
–80
t
DECAY
(
)
I
L
Figure 38. Output Enable/Disable
Figure 39. 31Equivalent Device Loading for AC
Measurements (Includes All Fixtures)
Figure 40. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS DRIVING
V
OH
(MEASURED) –
V
V
OL
(MEASURED) +
V
t
MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
2.0V
1.0V
V
OH
(MEASURED)
V
OL
(MEASURED)
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
OUTPUT STOPS DRIVING
t
ENA
t
DECAY
1.5V
30pF
TO
OUTPUT
PIN
50
INPUT
OR
OUTPUT
1.5V
1.5V
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