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參數資料
| 型號： | ADSP-21161NCCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數： | 21/60頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | ADSP-21161NCCA-100 |
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–21–
REV. A
ADSP-21161N
Use the exact timing information given. Do not attempt to derive
parameters from the addition or subtraction of others. While
addition or subtraction would yield meaningful results for an
individual device, the values given in this data sheet reflect sta-
tistical variations and worst cases. Consequently, it is not
meaningful to add parameters to derive longer times.
See
Figure 40 on Page 51
under Test Conditions for voltage
reference levels.
Switching characteristics specify how the processor changes its
signals. Circuitry external to the processor must be designed for
compatibility with these signal characteristics. Switching charac-
teristics describe what the processor will do in a given circum-
stance. Use switching characteristics to ensure that any timing
requirement of a device connected to the processor (such as
memory) is satisfied.
Timing requirements apply to signals that are controlled by
circuitry external to the processor, such as the data input for a
read operation. Timing requirements guarantee that the
processor operates correctly with other devices.
Power Dissipation
Total power dissipation has two components: one due to internal
circuitry and one due to the switching of external output drivers.
Internal power dissipation depends on the instruction execution
sequence and the data operands involved. Using the current spec-
ifications (I
DDINPEAK
, I
DDINHIGH
, I
DDINLOW
, I
DDIDLE
) from the
Electrical Characteristics
on Page 18
and the current-versus-
operation information in
Table 6
, the programmer can estimate
the ADSP-21161N’s internal power supply (V
DDINT
) input
current for a specific application, according to the following
formula:
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on:
The number of output pins that switch during each cycle
(
O
)
The maximum frequency at which they can switch (
f
)
Their load capacitance (
C
)
Their voltage swing (
V
DD
)
and is calculated by:
The load capacitance should include the processor package
capacitance (C
IN
). The switching frequency includes driving the
load high and then back low. At a maximum rate of 1/t
CK
,
address and data pins can drive high and low, while writing to a
SDRAM memory.
Example: Estimate
P
EXT
with the following assumptions:
A system with one bank of external memory (32 bit)
Two 1M 16 SDRAM chips are used, each with a load
of 10 pF (ignoring trace capacitance)
External Data Memory writes can occur every cycle at a
rate of 1/t
CK
with 50% of the pins switching
The bus cycle time is 50 MHz
The external SDRAM clock rate is 100 MHz
Ignoring SDRAM refresh cycles
Addresses are incremental and on the same page
The
P
EXT
equation is calculated for each class of pins that can
drive, as shown in
Table 7
.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation:
Where:
P
EXT
is from
Table 7
.
P
INT
is I
DDINT
× 1.8 V, using the calculation I
DDINT
listed in
Power
Dissipation on Page 21
.
P
PLL
is AI
DD
× 1.8 V, using the value for AI
DD
listed in the Electrical
Characteristics
on Page 18
.
% Peak
I
DDINPEAK
I
DDINHIGH
I
DDINLOW
I
I
DDINT
×
×
×
% High
% Low
--------------------------------------------------
Table 6. Operation Types Versus Input Current
Operation
Instruction Type
Instruction Fetch
Core Memory Access
2
Internal Memory DMA
External Memory DMA
Data bit pattern for core
memory access and DMA
Peak Activity
1
(I
DDINPEAK
)
Multifunction
Cache
2 per t
CK
cycle (DM
×
64 and PM
×
64)
1 per 2 t
CCLK
cycles
1 per external port cycle (
×
32)
Worst case
High Activity
1
(I
DDINHIGH
)
Multifunction
Internal Memory
1 per t
CK
cycle (DM
×
64)
1 per 2 t
CCLK
cycles
1 per external port cycle (
×
32)
Random
Low Activity
1
(I
DDINLOW
)
Single Function
Internal Memory
None
N/A
N/A
N/A
1
The state of the PEYEN bit (SIMD versus SISD mode) does not influence these calculations.
2
These assume a 2:1 core clock ratio. For more information on ratios and clocks (t
CK
and t
CCLK
), see the timing ratio definitions
on Page 20
.
P
EXT
O
C
×
V
DD
2
×
f
×
=
P
TOTAL
P
EXT
P
INT
P
PLL
+
+
=
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|---|---|
| ADSP-21161NKCA-100 | DSP Microcomputer |
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相關代理商/技術參數 |
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| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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