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參數資料
| 型號： | ADSP-21161NCCA-100 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理 |
| 英文描述： | DSP Microcomputer |
| 中文描述： | 48-BIT, 27.5 MHz, OTHER DSP, PBGA225 |
| 封裝： | 17 X 17 MM, MO-192AAF-2, BGA-225 |
| 文件頁數： | 15/60頁 |
| 文件大?。?/td> | 1019K |
| 代理商： | ADSP-21161NCCA-100 |
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–15–
REV. A
ADSP-21161N
FSx
I/O
Transmit or Receive Frame Sync
(Serial Ports 0, 1, 2, 3). The frame sync pulse initiates
shifting of serial data. This signal is either generated internally or externally. It can be active
high or low or an early or a late frame sync, in reference to the shifting of serial data.
Serial Peripheral Interface Clock Signal
. Driven by the master, this signal controls the
rate at which data is transferred. The master may transmit data at a variety of baud rates.
SPICLK cycles once for each bit transmitted. SPICLK is a gated clock that is active during
data transfers, only for the length of the transferred word. Slave devices ignore the serial
clock if the slave select input is driven inactive (HIGH). SPICLK is used to shift out and
shift in the data driven on the MISO and MOSI lines. The data is always shifted out on one
clock edge of the clock and sampled on the opposite edge of the clock. Clock polarity and
clock phase relative to data are programmable into the SPICTL control register and define
the transfer format. SPICLK has a 50 k
internal pull-up resistor.
Serial Peripheral Interface Slave Device Select
. An active low signal used to enable
slave devices. This input signal behaves like a chip select, and is provided by the master device
for the slave devices. In multimaster mode
SPIDS
signal can be asserted to a master device
to signal that an error has occurred, as some other device is also trying to be the master
device. If asserted low when the device is in master mode, it is considered a multimaster
error. For a single-master, multiple-slave configuration where FLAG3
–
0 are used, this pin
must be tied or pulled high to V
DDEXT
on the master device. For ADSP-21161N to ADSP-
21161N SPI interaction, any of the master ADSP-21161N’s FLAG3
–
0 pins can be used to
drive the
SPIDS
signal on the ADSP-21161N SPI slave device.
SPI Master Out Slave
. If the ADSP-21161N is configured as a master, the MOSI pin
becomes a data transmit (output) pin, transmitting output data. If the ADSP-21161N is
configured as a slave, the MOSI pin becomes a data receive (input) pin, receiving input data.
In an ADSP-21161N SPI interconnection, the data is shifted out from the MOSI output pin
of the master and shifted into the MOSI input(s) of the slave(s). MOSI has an internal pull-
up resistor.
SPI Master In Slave Out
. If the ADSP-21161N is configured as a master, the MISO pin
becomes a data receive (input) pin, receiving input data. If the ADSP-21161N is configured
as a slave, the MISO pin becomes a data transmit (output) pin, transmitting output data. In
an ADSP-21161N SPI interconnection, the data is shifted out from the MISO output pin
of the slave and shifted into the MISO input pin of the master. MISO has an internal pull-
up resistor. MISO can be configured as o/d by setting the OPD bit in the SPICTL register.
Note:
Only one slave is allowed to transmit data at any given time.
Link Port Data (Link Ports 0
–
1).
For silicon revisions 1.2 and higher, each LxDAT pin has a keeper latch that is enabled when
used as a data pin; or a 20 k
internal pull-down resistor that is enabled or disabled by the
LxPDRDE bit of the LCTL register.
For silicon revisions 0.3, 1.0, and 1.1 each LxDAT pin has a 50 k
internal pull-down resistor
that is enabled or disabled by the LxPDRDE bit of the LCTL register.
Note:
L1DAT7
–
0 are multiplexed with the DATA15
–
8 pins L0DAT7
–
0 are multiplexed with the
DATA7
–
0 pins. If link ports are disabled and are not used, these pins can be used as additional
data lines for executing instructions at up to the full clock rate from external memory. See
DATA47
–
16 for more information.
Link Port Clock
(Link Ports 0
–
1). Each LxCLK pin has an internal pull-down 50 k
resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
Link Port Acknowledge
(Link Ports 0
–
1). Each LxACK pin has an internal pull-down
50 k
resistor that is enabled or disabled by the LxPDRDE bit of the LCTL register.
EPROM Boot Select
. For a description of how this pin operates, see the table in the
BMS
pin description. This signal is a system configuration selection that should be hardwired.
Link Boot
. For a description of how this pin operates, see the table in the
BMS
pin
description. This signal is a system configuration selection that should be hardwired.
SPICLK
I/O
SPIDS
I
MOSI
I/O (o/d)
MISO
I/O (o/d)
LxDAT7
–
0
[DATA15
–
0]
I/O
[I/O/T]
LxCLK
I/O
LxACK
I/O
EBOOT
I
LBOOT
I
Table 2. Pin Function Descriptions (continued)
Pin
Type
Function
相關PDF資料 |
PDF描述 |
|---|---|
| ADSP-21161NKCA-100 | DSP Microcomputer |
| ADSP-21262SBBC-150 | Embedded Processor |
| ADSP-21262SBBCZ150 | Embedded Processor |
| ADSP-21262SKSTZ200 | SHARC Processor |
| ADSP-21262 | SHARC Processor |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ADSP-21161NCCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NKCA-100Z | 制造商:Analog Devices 功能描述: |
| ADSP-21161NKCAZ100 | 功能描述:IC DSP CONTROLLER 32BIT 225MBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-21161NYCAZ110 | 功能描述:IC DSP CONTROLLER 32BIT 225BGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:SHARC® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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