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參數資料
| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數： | 12/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561 |
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Rev. PrC
|
Page 12 of 52
|
April 2004
ADSP-BF561
Preliminary Technical Data
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-BF561
allows both the processor’s input voltage (V
DDINT
) and clock
frequency (f
CCLK
) to be dynamically controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
The Power Savings Factor is calculated as:
where the variables in the equations are:
f
CCLKNOM
is the nominal core clock frequency
f
CCLKRED
is the reduced core clock frequency
V
DDINTNOM
is the nominal internal supply voltage
V
DDINTRED
is the reduced internal supply voltage
T
NOM
is the duration running at f
CCLKNOM
T
RED
is the duration running at f
CCLKRED
The percent power savings is calculated as:
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply.
Figure 4
shows the typical external components
required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(V
DDEXT
) supplied. While in hibernation, V
DDEXT
can still be
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this powerdown state by assert-
ing RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
Table 4. ADSP-BF561 Power Domains
Power Domain
All internal logic
I/O
VDD Range
V
DDINT
V
DDEXT
Figure 4. Voltage Regulator Circuit
Power Savings Factor
f
CCLKNOM
---------------------
V
DDINTNOM
--------------------------
2
×
T
NOM
------------
×
=
% Power Savings
1
Power Savings Factor
–
(
)
100%
×
=
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| adsp-bf5615bbz600 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述: |
| ADSP-BF561KBCZ-600 | 制造商:Analog Devices 功能描述: |
| ADSP-BF561SBB500 | 功能描述:IC PROCESSOR 500MHZ 297PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SBB600 | 功能描述:IC DSP 32BIT 600MHZ 297-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SBB600 | 制造商:Analog Devices 功能描述:IC MULTIPROCESSOR |
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