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參數資料
| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數： | 5/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561 |
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ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 5 of 52
|
April 2004
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the bandwidth of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low-latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 KB L2 SRAM memory.
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Figure 3. Memory Map
RESERVED
ASYNCMEMORYBANK3
ASYNCMEMORYBANK2
ASYNCMEMORYBANK1
ASYNCMEMORYBANK0
0xFF800000
0xFF701000
0xFF700000
0xFF614000
0xFF504000
0xFF500000
0xFF408000
0xFF404000
0xFF400000
0xFF610000
0xFF604000
0xFF600000
0xFF508000
L1SCRATCHPADSRAM(4K)
RESERVED
L1INSTRUCTIONSRAMCACHE(16K)
RESERVED
L1INSTRUCTIONSRAM(16K)
RESERVED
L1DATABANKBSRAMCACHE(16K)
L1DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAMCACHE(16K)
L1DATABANKASRAM(16K)
COREAMEMORYMAP
COREBMEMORYMAP
COREMMRREGSTERS
COREMMRREGISTERS
SYSTEMMMRREGSTERS
L1SCRATCHPADSRAM(4K)
RESERVED
L1INSTRUCTIONSRAMCACHE(16K)
RESERVED
L1INSTRUCTIONSRAM(16K)
L1DATABANKBSRAMCACHE(16K)
L1DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAMCACHE(16K)
L1DATABANKASRAM(16K)
L2SRAM(128K)
RESERVED
BOOTROM
RESERVED
SDRAMBANK3
SDRAMBANK2
SDRAMBANK1
SDRAMBANK0
0xFFE00000
0xFFC00000
0xFFB01000
0xFFB00000
0xFFA14000
0xFFA10000
0xFFA04000
0xFFA00000
0xFF908000
0xFF904000
0xFF900000
0xFF808000
0xFF804000
0xFEB20000
0xFEB00000
0xEF004000
0xEF000000
0x30000000
0x2C000000
0x28000000
0x24000000
0x20000000
0x00000000
INTERNALMEMORY
EXTERNALMEMORY
0xFFFFFFFF
TopoflastSDRAMpage
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0xFF800000
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| ADSP-BF561SBB600 | 功能描述:IC DSP 32BIT 600MHZ 297-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
| ADSP-BF561SBB600 | 制造商:Analog Devices 功能描述:IC MULTIPROCESSOR |
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