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參數資料
| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數： | 13/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561 |
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ADSP-BF561
Preliminary Technical Data
Rev. PrC
|
Page 13 of 52
|
April 2004
CLOCK SIGNALS
The ADSP-BF561 can be clocked by an external crystal, a sine
wave input, or a buffered, shaped clock derived from an external
clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the speci-
fied frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be
left
unconnected.
Alternatively, because the ADSP-BF561 includes an on-chip
oscillator circuit, an external crystal may be used. The crystal
should be connected across the CLKIN and XTAL pins, with
two capacitors connected as shown in
Figure 5
Capacitor values are dependent on crystal type and should be
specified by the crystal manufacturer. A parallel-resonant, fun-
damental frequency, microprocessor-grade crystal should be
used.
As shown in
Figure 6
, the core clock (CCLK) and system
peripheral clock (SCLK) are derived from the input clock
(CLKIN) signal. An on-chip PLL is capable of multiplying the
CLKIN signal by a user programmable 1x to 63x multiplication
factor. The default multiplier is 10x, but it can be modified by a
software instruction sequence. On-the-fly frequency changes
can be effected by simply writing to the PLL_DIV register.
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
Table 5
illustrates typical system clock ratios:
The maximum frequency of the system clock is f
SCLK
. Note that
the divisor ratio must be chosen to limit the system clock fre-
quency to its maximum of f
SCLK
. The SSEL value can be changed
dynamically without any PLL lock latencies by writing the
appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL[1–0] bits of the PLL_DIV regis-
ter. Supported CCLK divider ratios are 1, 2, 4, and 8, as shown
in
Table 6
. This programmable core clock capability is useful for
fast core frequency modifications.
BOOTING MODES
The ADSP-BF561 has three mechanisms (listed in
Table 7
) for
automatically loading internal L1 instruction memory after a
reset. A fourth mode is provided to execute from external mem-
ory, bypassing the boot sequence.
Figure 5. External Crystal Connections
Figure 6. Frequency Modification Methods
CLKIN
CLKOUT
XTAL
PLL
1
×
- 63
×
×
1:15
×
1, 2, 4, 8
VCO
SCLK
≤
CCLK
SCLK
≤
133MHZ
CLKIN
“FINE” ADJUSTMENT
REQUIRES PLL SEQUENCING
“COARSE” ADJUSTMENT
ON-THE-FLY
CCLK
SCLK
Table 5. Example System Clock Ratios
Signal Name
SSEL[3–0]
Divider Ratio
VCO/SCLK
Example Frequency Ratios
(MHz)
VCO
100
300
500
SCLK
100
50
50
0001
0110
1010
1:1
6:1
10:1
Table 6. Core Clock Ratios
Signal Name
CSEL[1–0]
Divider Ratio
VCO/CCLK
Example Frequency Ratios
VCO
500
500
200
200
CCLK
500
250
50
25
00
01
10
11
1:1
2:1
4:1
8:1
Table 7. Booting Modes
BMODE1–0
00
Description
Execute from 16-bit external memory (Bypass
Boot ROM)
Boot from 8/16-bit flash
Reserved
Boot from SPI serial ROM (16-bit address
range)
01
10
11
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| ADSP-BF561SBB600 | 功能描述:IC DSP 32BIT 600MHZ 297-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - DSP（數字式信號處理器） 系列:Blackfin® 標準包裝:2 系列:StarCore 類型:SC140 內核 接口:DSI，以太網，RS-232 時鐘速率:400MHz 非易失內存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:431-BFBGA，FCBGA 供應商設備封裝:431-FCPBGA（20x20） 包裝:托盤 |
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