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參數資料
| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數： | 42/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561 |
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Rev. PrC
|
Page 42 of 52
|
April 2004
ADSP-BF561
Preliminary Technical Data
POWER DISSIPATION
Total power dissipation has two components, one due to inter-
nal circuitry (P
INT
) and one due to the switching of external
output drivers (P
EXT
).
Table 30
shows the power dissipation for
internal circuitry (V
DDINT
). Internal power dissipation is depen-
dent on the instruction execution sequence and the data
operands involved.
The external component of total power dissipation is caused by
the switching of output pins. Its magnitude depends on
The number of output pins that switch during each cycle
(O)
The maximum frequency at which they can switch (f)
Their load capacitance (C)
Their voltage swing (V
DDEXT
)
The external component is calculated using:
The frequency f includes driving the load high and then back
low. For example: DATA15–0 pins can drive high and low at a
maximum rate of 1/(23t
SCLK
) while in SDRAM burst mode.
A typical power consumption can now be calculated for these
conditions by adding a typical internal power dissipation.
Note that the conditions causing a worst-case P
EXT
differ from
those causing a worst-case P
INT
. Maximum P
INT
cannot occur
while 100% of the output pins are switching from all ones (1s) to
all zeros (0s). Note also that it is not common for an application
to have 100%,or even 50%, of the outputs switching
simultaneously.
OUTPUT DRIVE CURRENTS
Figure 22
shows typical I-V characteristics for the output driv-
ers of the ADSP-BF561. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Tim-
ing Specifications on Page 22
. These include output disable
time, output enable time, and capacitive loading. The timing
specifications for the DSP apply for the voltage reference levels
in
Figure 23
.
Table 30. Internal Power Dissipation
Test Conditions
1
1
I
DD
data is specified for typical process parameters. All data at 25oC.
2
Processor executing 75% dual Mac, 25% ADD with moderate data bus
activity.
3
See the
ADSP-BF53x Blackfin Processor Hardware Reference Manual
for
definitions of Sleep and Deep Sleep operating modes.
4
Measured at V
DDEXT
= 3.65V with voltage regulator off (V
DDINT
= 0V).
Parameter f
CCLK
=
50 MHz
V
DDINT
=
0.8 V
TBD
TBD
TBD
f
CCLK
=
400 MHz
V
DDINT
=
1.2 V
TBD
TBD
TBD
f
CCLK
=
600 MHz
V
DDINT
=
1.2 V
520
TBD
70
f
CCLK
=
600 MHz
V
DDINT
=
1.35 V
TBD
TBD
TBD
Unit
I
DDTYP
2
I
DDSLEEP
3
I
DDDEEPSLEEP
3
mA
mA
mA
I
DDHI-
BERNATE
4
TBD
TBD
TBD
TBD
A
Figure 22. ADSP-BF561 Typical Drive
P
EXT
O
C
×
V
2
DD
×
f
×
=
P
Total
P
EXT
I
DD
V
DDINT
×
(
)
+
=
SOURCE (VDDEXT) VOLTAGE - V
120
-20
-80
0
3.5
0.5
1
1.5
2
2.5
3
100
0
-40
-60
60
20
80
40
-100
-120
S
TBD
Figure 23. Voltage Reference Levels for AC Measurements (Except Output
Enable/Disable)
INPUT
OR
OUTPUT
1.5V
1.5V
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