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| 型號： | ADSP-BF561 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronous 4-Bit Up/Down Binary Counters With Dual Clock and Clear 16-PDIP 0 to 70 |
| 中文描述： | 嵌入式Blackfin處理器的對稱多處理器 |
| 文件頁數(shù)： | 2/52頁 |
| 文件大小： | 508K |
| 代理商： | ADSP-BF561 |
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Rev. PrC
|
Page 2 of 52
|
April 2004
ADSP-BF561
Preliminary Technical Data
TABLE OF CONTENTS
General Description ................................................. 3
Portable Low-Power Architecture ............................. 3
Blackfin Processor Core .......................................... 3
Memory Architecture ............................................ 4
Internal (On-chip) Memory ................................. 4
External (Off-Chip) Memory ................................ 5
I/O Memory Space ............................................. 6
Booting ........................................................... 6
Event Handling ................................................. 6
Core Event Controller (CEC) ................................ 6
System Interrupt Controller (SIC) .......................... 6
Event Control ................................................... 7
DMA Controllers .................................................. 8
WatchDog Timers ................................................ 8
Serial Ports (SPORTs) ............................................ 9
Serial Peripheral Interface (SPI) Ports ........................ 9
UART Port .......................................................... 9
Programmable Flags (PFx) .................................... 10
Timers ............................................................. 10
Parallel Peripheral Interface ................................... 10
General Purpose Mode Descriptions .................... 10
Input Mode .................................................... 10
ITU -R 656 Mode Descriptions ........................... 10
Active Video Only Mode ................................... 10
Vertical Blanking Interval Mode .......................... 11
Entire Field Mode ............................................ 11
Dynamic Power Management ................................ 11
Full-On Operating Mode – Maximum Performance . 11
Active Operating Mode – Moderate Power Savings .. 11
Hibernate Operating Mode—Maximum Static Power
Savings ....................................................... 11
Sleep Operating Mode – High Power Savings ......... 11
Deep Sleep Operating Mode – Max. Power Savings .. 11
Power Savings ................................................. 12
Voltage Regulation .............................................. 12
Clock Signals ..................................................... 13
Booting Modes ................................................... 13
Instruction Set Description ................................... 14
Development Tools .............................................. 14
Designing an Emulator-Compatible
Processor Board (Target) ................................... 15
Additional Information ........................................ 15
Pin Descriptions .................................................... 16
Specifications ........................................................ 20
Recommended Operating Conditions ...................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings ................................... 21
ESD Sensitivity ................................................... 21
Timing Specifications ........................................... 22
Clock and Reset Timing ..................................... 23
Asynchronous Memory Read Cycle Timing ............ 24
Asynchronous Memory Write Cycle Timing ........... 25
SDRAM Interface Timing .................................. 26
External Port Bus Request and Grant Cycle Timing .. 27
Parallel Peripheral Interface Timing ..................... 28
Serial Ports ..................................................... 29
Serial Peripheral Interface (SPI) Port—Master Timing 34
Serial Peripheral Interface (SPI) Port—Slave Timing . 36
Universal Asynchronous Receiver-Transmitter (UART)
Port—Receive and Transmit Timing .................. 38
Timer Cycle Timing .......................................... 39
Programmable Flags Cycle Timing ....................... 40
JTAG Test And Emulation Port Timing ................. 41
Power Dissipation ............................................... 42
Output Drive Currents ......................................... 42
Test Conditions .................................................. 42
Output Enable Time ......................................... 43
Output Disable Time ......................................... 43
Example System Hold Time Calculation ................... 43
Capacitive Loading .............................................. 44
256-ball MBGA Pin Configurations ............................ 45
297-ball PBGA Pin Configurations ............................. 47
Outline Dimensions ................................................ 50
Outline Dimensions ................................................ 51
Ordering Guide ..................................................... 51
REVISION HISTORY
Revision PrC:
Edits made to pinlists and timing specification.
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