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參數資料
型號: ISP1362EE
廠商: NXP SEMICONDUCTORS
元件分類: 總線控制器
英文描述: Single-chip Universal Serial Bus On-The-Go controller
中文描述: UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
封裝: 6 X 6 MM, 0.80 HEIGHT, PLASTIC, MO-195, SOT-543-1, TFBGA-64
文件頁數: 117/150頁
文件大小: 647K
代理商: ISP1362EE
Philips Semiconductors
ISP1362
Single-chip USB OTG controller
Product data
Rev. 03
06 January 2004
117 of 150
9397 750 12337
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Code (Hex): C2/C3
write or read InterruptEnable register
Transaction
write or read 4 bytes (code or data)
16.1.6
DcDMACon
fi
guration (R/W: F1H/F0H)
This command de
fi
nes the DMA con
fi
guration of the DC and enables or disables
DMA transfers. The command accesses the DcDMACon
fi
guration register, which
consists of two bytes. The bit allocation is given in
Table 118
. A bus reset will clear
bit DMAEN (DMA disabled), all other bits remain unchanged.
Code (Hex): F0/F1
write or read DMA Con
fi
guration
Transaction
write or read 2 bytes (code or data)
Table 116: DcInterruptEnable register: bit allocation
Bit
31
Symbol
Reset
-
Access
-
Bit
23
Symbol
IEP14
Reset
0
Access
R/W
Bit
15
Symbol
IEP6
Reset
0
Access
R/W
Bit
7
Symbol
reserved
Reset
-
Access
-
30
29
28
27
26
25
24
reserved
-
-
-
-
-
-
-
-
-
-
-
-
-
-
22
21
20
19
18
IEP9
0
R/W
10
IEP1
0
R/W
2
IESUSP
0
R/W
17
IEP8
0
R/W
9
IEP0IN
0
R/W
1
IERESM
0
R/W
16
IEP7
0
R/W
8
IEP0OUT
0
R/W
0
IERST
0
R/W
IEP13
0
R/W
14
IEP5
0
R/W
6
SP_IEEOT
0
R/W
IEP12
0
R/W
13
IEP4
0
R/W
5
IEPSOF
0
R/W
IEP11
0
R/W
12
IEP3
0
R/W
4
IESOF
0
R/W
IEP10
0
R/W
11
IEP2
0
R/W
3
IEEOT
0
R/W
Table 117: DcInterruptEnable register: bit description
Bit
Symbol
31 to 24
-
23 to 10
IEP14 to IEP1
9
IEP0IN
8
IEP0OUT
7
-
6
SP_IEEOT
5
IEPSOF
4
IESOF
3
IEEOT
2
IESUSP
1
IERESM
0
IERST
Description
reserved; must write logic 0
Logic 1 enables interrupts from the indicated endpoint.
Logic 1 enables interrupts from the control IN endpoint.
Logic 1 enables interrupts from the control OUT endpoint.
reserved
Logic 1 enables interrupt upon detection of a short packet.
Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF.
Logic 1 enables interrupt upon the SOF detection.
Logic 1 enables interrupt upon the EOT detection.
Logic 1 enables interrupt upon detection of a
suspend
state.
Logic 1 enables interrupt upon detection of a
resume
state.
Logic 1 enables interrupt upon detection of a bus reset.
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ISP1362EE,551 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
ISP1362EE,557 功能描述:USB 接口集成電路 DO NOT USE ORDER -T PART RoHS:否 制造商:Cypress Semiconductor 產品:USB 2.0 數據速率: 接口類型:SPI 工作電源電壓:3.15 V to 3.45 V 工作電源電流: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:WLCSP-20
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