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| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁(yè)數(shù)： | 105/122頁(yè) |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
REGISTER SUMMARY
MOTOROLA
B-5
CIE1 — Queue 1 Completion Interrupt Enable
0 = Disable the queue completion interrupt associated with queue 1.
1 = Enable an interrupt after the conversion of the sample requested by the last
CCW in queue 1.
PIE1 — Queue 1 Pause Interrupt Enable
0 = Disable the pause interrupt associated with queue 1.
1 = Enable an interrupt after the conversion of the sample requested by a CCW in
queue 1 which has the pause bit set.
SSE1 — Queue 1 Single-Scan Enable Bit
0 = Trigger events are not accepted for single-scan modes.
1 = Accept a trigger event to start queue 1 in a single-scan mode.
MQ1[10:8] — Queue 1 Operating Mode
The MQ1 field selects the queue operating mode for queue 1.
Table B-4
shows the
bits in the MQ1 field which enable different queue 1 operating modes.
Table B-3 Prescaler Clock Low Times
PSL[2:0]
000
001
010
011
100
101
110
111
QCLK Low Time
1 System Clock Cycle
2 System Clock Cycles
3 System Clock Cycles
4 System Clock Cycles
5 System Clock Cycles
6 System Clock Cycles
7 System Clock Cycles
8 System Clock Cycles
QACR1 —
Control Register 1
$####0C
15
CIE1
RESET:
0
14
PIE1
13
12
NOT USED
11
10
9
8
7
6
5
4
NOT USED
3
2
1
0
SSE1
MQ1
0
0
0
0
0
Table B-4 Queue 1 Operating Modes
MQ1[10:8]
000
001
010
011
100
101
110
111
Operating Modes
Disabled mode, conversions do not occur
Software triggered single-scan mode (started with SSE1)
External trigger rising edge single-scan mode (on ETRIG1 pin)
External trigger falling edge single-scan mode (on ETRIG1 pin)
Reserved mode, conversions do not occur
Continuous-scan software triggered mode
External trigger rising edge continuous-scan mode (on ETRIG1 pin)
External trigger falling edge continuous-scan mode (on ETRIG1 pin)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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