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| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數(shù)字轉(zhuǎn)換器參考手冊 |
| 文件頁數(shù)： | 33/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
PIN CONNECTION CONSIDERATIONS
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
5-1
SECTION 5 PIN CONNECTION CONSIDERATIONS
The QADC requires accurate, noise-free input signals for proper operation. This sec-
tion discusses the design of external circuitry to maximize QADC performance.
5.1 Analog Reference Pins
No A/D converter can be more accurate than its analog reference. Any noise in the
reference can result in at least that much error in a conversion. The reference for the
QADC, supplied by pins V
RH
and V
RL
, should be low-pass filtered from its source to
obtain a noise-free, clean signal. In many cases, simple capacitive bypassing may suf-
fice. In extreme cases, inductors or ferrite beads may be necessary if noise or RF en-
ergy is present. Series resistance is not advisable since there is an effective DC
current requirement from the reference voltage by the internal resistor string in the RC
DAC array. External resistance may introduce error in this architecture under certain
conditions. Any series devices in the filter network should contain a minimum amount
of DC resistance.
For accurate conversion results, the analog reference voltages must be within the lim-
its defined by V
DDA
and V
SSA
, as explained in the following subsection.
5.2 Analog Power Pins
The analog supply pins (V
DDA
and V
SSA
) define the limits of the analog reference volt-
ages (V
RH
and V
RL
) and of the analog multiplexer inputs.
Figure 5-1
is a diagram of
the analog input circuitry.
F
Freescale Semiconductor, Inc.
n
.
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