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參數資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數字轉換器參考手冊 |
| 文件頁數： | 38/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
5-6
PIN CONNECTION CONSIDERATIONS
For More Information On This Product,
Go to: www.freescale.com
QADC
REFERENCE MANUAL
where:
V
STRESS
= Adjustable voltage source
V
BE
= Parasitic bipolar base/emitter voltage (refer to V
NEGCLAMP
in
AP-
PENDIX A ELECTRICAL CHARACTERISTICS
)
R
STRESS
= Source impedance (10K resistor in
Figure 5-4
on stressed
channel)
The current into (I
IN
) the neighboring pin is determined by the 1/K
N
(Gain) of the para-
sitic bipolar transistor (1/K
N
1).
One way to minimize the impact of stress conditions on the QADC is to apply voltage
limiting circuits such as diodes to supply and ground. However, leakage from such cir-
cuits and the potential influence on the sampled voltage to be converted must be con-
sidered. Refer to
Figure 5-5
.
Figure 5-5 Voltage Limiting Diodes in a Negative Stress Circuit
Another method for minimizing the impact of stress conditions on the QADC is to stra-
tegically allocate QADC inputs so that the lower accuracy inputs are adjacent to the
inputs most likely to see stress conditions.
Finally, suitable source impedances should be selected to meet design goals and min-
imize the effect of stress conditions.
5.5 Analog Input Considerations
The source impedance of the analog signal to be measured and any intermediate fil-
tering should be considered whether external multiplexing is used or not.
Figure 5-6
shows the connection of eight typical analog signal sources to one QADC analog input
pin through a separate multiplexer chip. Also, an example of an analog signal source
connected directly to a QADC analog input channel is displayed.
I
OUT
V
R
STRESS
BE
------------------------------V
=
QADC NEG STRESS CONN
VDD
R
kR
TO DEVICE
EXTERNAL VOLTAGE
VSS
F
Freescale Semiconductor, Inc.
n
.
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