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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 75/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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QADC
REFERENCE MANUAL
DIGITAL CONTROL
MOTOROLA
7-29
The end of queue 1 is implied by the beginning of queue 2, which is specified in
the BQ2 field in QACR2.
The physical end of the queue RAM space defines the end of either queue.
When any of the end-of-queue conditions is recognized, a queue completion flag is
set, and if enabled, an interrupt is issued to the software. The following situations pre-
maturely terminate queue execution:
Since queue 1 is higher in priority than queue 2, when a trigger event occurs on
queue 1 during queue 2 execution, the execution of queue 2 is suspended by
aborting the execution of the CCW in progress, and the queue 1 execution be-
gins. When queue 1 execution is completed, queue 2 conversions restart with the
first CCW entry in queue 2 or the first CCW of the queue 2 subqueue being exe-
cuted when queue 2 was suspended. Alternately, conversions can restart with the
aborted queue 2 CCW entry. The resume (RES) field in QACR2 allows the soft-
ware to select where queue 2 begins after suspension. By choosing to re-execute
all of the suspended queue 2 queue and subqueue CCWs, all of the samples are
guaranteed to have been taken during the same scan pass. However, a high trig-
ger event rate for queue 1 can prohibit the completion of queue 2. If this occurs,
the software may choose to begin execution of queue 2 with the aborted CCW
entry.
Software can change the queue operating mode to disabled mode. Any current
conversion taking place for that queue is aborted. Putting a queue into the dis-
abled mode does not power down the converter.
Software can change the queue operating mode to another valid mode. Any cur-
rent conversion taking place for that queue is aborted. The queue restarts at the
beginning of the queue, once an appropriate trigger event occurs.
For low power operation, software can set the stop mode bit to prepare the mod-
ule for a loss of clocks. The QADC aborts any conversion in progress when the
stop mode is entered.
When the freeze enable bit is set by software and the IMB internal FREEZE line
is asserted, the QADC freezes at the end of the current conversion. When internal
FREEZE is negated, the QADC resumes queue execution beginning with the next
CCW entry. Refer to paragraph 3.3.2 in
SECTION 3 CONFIGURATION AND
CONTROL
for more information.
CCW —
Conversion Command Word Table
P — Pause
The pause bit allows software to create sub-queues within queue 1 and queue 2. The
QADC performs the conversion specified by the CCW with the pause bit set, and then
the queue enters the pause state. Another trigger event causes execution to continue
from the pause to the next CCW.
0 = Do not enter the pause state after execution of the current CCW.
1 = Enter the pause state after execution of the current CCW.
$####30–$####7E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
NOT USED
P
BYP
IST
CHAN
RESET:
U
U
U
U
U
U
U
U
U
U
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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