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參數資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數字轉換器參考手冊 |
| 文件頁數： | 16/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
1-4
OVERVIEW
QADC
REFERENCE MANUAL
other information about the operation of the QADC. Refer to
SUMMARY
for more information.
APPENDIX B REGISTER
The QADC has three global registers for configuring module operation: the module
configuration register (QADCMCR), the interrupt register (QADCINT), and a test reg-
ister (QADCTEST). The global registers are always defined to be in supervisor-only
data space. When the CPU supports the supervisor/user address data space desig-
nations, software can establish the global registers to be in supervisor data space and
the remaining registers and tables to be in user space.
All QADC analog channel/port pins that are not used for analog input channels can be
used as digital port pins. Port values are read/written by accessing the port A and B
data registers (PORTQA and PORTQB). The digital port pins are specified as inputs
or outputs by programming the port data direction register (DDRQA). Only port A uses
open drain pull-down output drivers.
The remaining four registers in the control register block control the operation of the
queuing mechanism, and provide a means of monitoring the operation of the QADC.
Control register 0 (QACR0) contains hardware configuration information. Control reg-
ister 1 (QACR1) is associated with queue 1, and control register 2 (QACR2) is asso-
ciated with queue 2. The status register (QASR) provides visibility on the status of
each queue and the particular conversion that is in progress.
Following the register block in the address map is the CCW table. There are 40 words
to hold the desired analog conversion sequences. Each CCW is a 16-bit word, with ten
implemented bits in four fields. Refer to
APPENDIX B REGISTER SUMMARY
more information.
for
The final block of address space belongs to the result word table, which appears in
three places in the memory map. Each result word table location holds one 10-bit con-
version value. The software selects one of three data formats, which map the 10-bit
result onto the 16-bit data bus by reading the address which produces the desired
alignment. The first address block presents the result data in right justified format, the
second block is presented in left justified signed format, and the third is presented in
left justified unsigned format. Refer to
APPENDIX B REGISTER SUMMARY
information.
for more
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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