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參數資料
| 型號： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊模擬到數字轉換器參考手冊 |
| 文件頁數： | 84/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
8-4
INTERRUPTS
QADC
REFERENCE MANUAL
IRL1 determines the priority of both queue 1 interrupt sources. IRL2 determines the
priority of both queue 2 interrupt sources. As a result, queue 1 and queue 2 can have
different priorities in the overall interrupt hierarchy of the MCU. The QADC also has an
internal interrupt request prioritization. Queue 1 interrupt requests are higher in priority
than queue 2 requests, and completion flag requests are higher in priority than pause
requests.
8.6 Interrupt Arbitration
After queue 1 or queue 2 issues an interrupt service request, the CPU performs an in-
terrupt acknowledge cycle. During the interrupt acknowledge cycle, the CPU identifies
the interrupt request level being acknowledged by placing it on the address bus. The
QADC compares the acknowledged interrupt level with IRL1 and IRL2 values, and re-
sponds if the values match.
The same interrupt priority level can be assigned to more than one module. For exam-
ple, the QADC and the queued serial module (QSM) can both be assigned priority five.
If the QADC and the QSM request interrupt service simultaneously, then the interrupt
arbitration (IARB) fields in the respective module configuration registers are used to
determine which module is serviced first.
The IARB field is essentially a second-level priority in case of a tie. Each module that
can request interrupt service has an IARB field. Arbitration is performed by means of
serial contention of IARB field bit values. Arbitration always takes place, even when a
single source requests service.
IARB fields contain four bits. An IARB value of $1111 has the highest arbitration prior-
ity, and %0001 has the lowest. If a module with an IARB field value of %0000 requests
interrupt service, the CPU processes a spurious interrupt exception because the mod-
ule requesting the interrupt service cannot confirm that it made the request. Initializa-
tion software must assign each IARB field a unique non-zero value in order to
implement the arbitration scheme. If two or more modules are assigned the same non-
zero IARB field value, operation is undefined when interrupts of the same priority level
are recognized.
8.7 Interrupt Vectors
When the QADC is the only module with an interrupt request pending at the level being
acknowledged, or when the QADC IARB value is higher than that of other modules
with requests pending at the acknowledged level, the QADC responds to the interrupt
acknowledge cycle with an 8-bit interrupt vector number. The CPU uses the vector
number to calculate a displacement into the exception vector table, then uses the vec-
tor at that location to jump to an interrupt service routine.
The interrupt vector base (IVB) field establishes the six high-order bits of the 8-bit in-
terrupt vector number, and the QADC provides two low-order bits which correspond to
one of the four internal QADC interrupt sources.
Figure 8-2
shows the format of the interrupt vector, and lists the binary coding of the
two low-order bits for the four QADC interrupt sources.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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