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參數(shù)資料
| 型號(hào)： | QADCRM |
| 英文描述： | Queued Analog-to-Digital Converter Reference Manual |
| 中文描述： | 排隊(duì)模擬到數(shù)字轉(zhuǎn)換器參考手冊(cè) |
| 文件頁數(shù)： | 6/122頁 |
| 文件大小： | 940K |
| 代理商： | QADCRM |
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MOTOROLA
vi
TABLE OF CONTENTS
QADC
REFERENCE MANUAL
(Continued)
Title
Paragraph
Page
TABLE OF CONTENTS
SECTION 5 PIN CONNECTION CONSIDERATIONS
5.1
5.2
5.3
5.4
5.5
5.6
5.6.1
5.6.2
Analog Reference Pins ..............................................................................5-1
Analog Power Pins ....................................................................................5-1
Analog Supply Filtering and Grounding .....................................................5-3
Accommodating Positive/Negative Stress Conditions ...............................5-5
Analog Input Considerations .....................................................................5-6
Analog Input Pins ......................................................................................5-8
Settling Time for the External Circuit .................................................5-9
Error Resulting from Leakage .........................................................5-10
SECTION 6 ANALOG SUBSYSTEM
6.1
6.1.1
6.1.1.1
6.2
6.3
6.4
6.5
Analog-to-Digital Converter Operation ......................................................6-1
Conversion Cycle Times ...................................................................6-2
Amplifier Bypass Mode Conversion Timing ..............................6-2
Front-End Analog Multiplexer ....................................................................6-3
Digital to Analog Converter Array ..............................................................6-3
Comparator ...............................................................................................6-4
Successive Approximation Register ..........................................................6-4
SECTION 7 DIGITAL CONTROL
7.1
7.2
7.3
7.3.1
7.3.2
7.3.2.1
7.3.2.2
7.3.2.3
7.3.3
7.3.3.1
7.3.3.2
7.3.3.3
7.4
7.5
7.6
7.6.1
7.6.2
7.6.3
7.6.4
Queue Priority ...........................................................................................7-1
Boundary Conditions .................................................................................7-3
Scan Modes ..............................................................................................7-4
Disabled Mode and Reserved Mode .................................................7-4
Single-Scan Modes ...........................................................................7-4
Software Initiated Single-Scan Mode ........................................7-5
External Trigger Single-Scan Mode ..........................................7-6
Interval Timer Single-Scan Mode ..............................................7-6
Continuous-Scan Modes ...................................................................7-7
Software Initiated Continuous-Scan Mode ................................7-8
External Trigger Continuous-Scan Mode ..................................7-9
Periodic Timer Continuous-Scan Mode ....................................7-9
QADC Clock (QCLK) Generation ..............................................................7-9
Periodic/Interval Timer ............................................................................7-13
Control and Status Registers ..................................................................7-14
Control Register 0 ...........................................................................7-14
Control Register 1 ...........................................................................7-16
Control Register 2 ...........................................................................7-17
Status Register ................................................................................7-20
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
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