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SLAS659 – NOVEMBER 2009
5.6
Audio DAC and Audio Analog Outputs
The mono audio DAC consists of a digital audio processing block, a digital interpolation filter, a digital
delta-sigma modulator, and an analog reconstruction filter. The high oversampling ratio (normally DOSR is
between 32 and 128) exhibits good dynamic range by ensuring that the quantization noise generated
within the delta-sigma modulator stays outside of the audio frequency band. Audio analog outputs include
mono headphone/lineout and mono class-D speaker outputs. Because the TLV320DAC3120 contains a
mono DAC, it inputs the mono data from the left channel, the right channel, or a mix of the left and right
channels as [(L + R) ÷ 2], selected by page 0 / register 63, bits D5–D4. See
Figure 1-1 for the signal flow.
5.6.1
DAC
The TLV320DAC3120 mono audio DAC supports data rates from 8 kHz to 192 kHz. The audio channel of
the mono DAC consists of a signal-processing engine with fixed processing blocks, a programmable
miniDSP, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction
filter. The DAC is designed to provide enhanced performance at low sampling rates through increased
oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma
modulator and observed in the signal images strongly suppressed within the audio band to beyond 20
kHz.
To
handle
multiple
input
rates
and
optimize
power
dissipation
and
performance,
the
TLV320DAC3120 allows the system designer to program the oversampling rates over a wide range from 1
to 1024 by configuring page 0 / register 13 and page 0 / register 14. The system designer can choose
higher oversampling ratios for lower input data rates and lower oversampling ratios for higher input data
rates.
The TLV320DAC3120 DAC channel includes a built-in digital interpolation filter to generate oversampled
data for the delta-sigma modulator. The interpolation filter can be chosen from three different types,
depending on required frequency response, group delay, and sampling rate.
DAC power up is controlled by writing to page 0 / register 63, bit D7 for the mono channel. The
mono-channel DAC clipping flag is provided as a read-only bit on page 0 / register 39, bit D7.
5.6.1.1
DAC Processing Blocks
The TLV320DAC3120 implements signal-processing capabilities and interpolation filtering via processing
blocks. These fixed processing blocks give users the choice of how much and what type of signal
processing they may use and which interpolation filter is applied.
The choices among these processing blocks allows the system designer to balance power conservation
and signal-processing flexibility.
Table 5-6 gives an overview of all available processing blocks of the DAC
channel and their properties. The resource-class column gives an approximate indication of power
consumption for the digital (DVDD) supply; however, based on the out-of-band noise spectrum, the analog
power consumption of the drivers (HPVDD) may differ.
The signal-processing blocks available are:
First-order IIR
Scalable number of biquad filters
The processing blocks are tuned for common cases and can achieve high image rejection or low group
delay in combination with various signal-processing effects such as audio effects and frequency shaping.
The available first-order IIR and biquad filters have fully user-programmable coefficients.
Copyright 2009, Texas Instruments Incorporated
APPLICATION INFORMATION
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