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參數資料
| 型號： | TLV320DAC3120IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數： | 32/110頁 |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBR |
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SLAS659 – NOVEMBER 2009
www.ti.com
0.125 dB per input sample, either up or down, until the desired volume is reached. The rate of
soft-stepping can be slowed to one step per two input samples by writing to page 0 / register 63, bits
D1–D0. Note that the default source for volume-control level settings is controlled by register writes to
page 0 / register 65. Use of the VOL/MICDET pin to control the DAC volume is ignored until the
volume-control source selected has been changed to pin control (page 0 / register 116, bit D7 = 1). This
functionality is shown in Figure 1-1.
During soft-stepping, the host does not receive a signal when the DAC has been completely muted. This
may be important if the host must mute the DAC before making a significant change, such as changing
sample rates. In order to help with this situation, the device provides a flag back to the host via a
read-only register, page 0 / register 38, bit D4 for the mono channel. This information alerts the host when
the part has completed the soft-stepping, and the actual volume has reached the desired volume level.
The soft-stepping feature can be disabled by writing to page 0 / register 63, bits D1–D0.
If soft-stepping is enabled, the CODEC_CLKIN signal should be kept active until the DAC power-up flag is
cleared. When this flag is cleared, the internal DAC soft-stepping process is complete, and
CODEC_CLKIN can be stopped if desired. (The analog volume control can be ramped down using an
internal oscillator.)
5.6.3
Volume-Control Pin
The range of voltages used by the 7-bit SAR ADC is shown in the Electrical Characteristics table.
The volume-control pin is not enabled by default, but it can be enabled by writing 1 to page 0 /
register 116, bit D7. The default DAC volume control uses software control of the volume, which occurs if
page 0 / register 116, bit D7 = 0. Soft-stepping the volume level is set up by writing to page 0 / register 63,
bits D1–D0.
When the volume-pin function is used, a 7-bit Vol ADC reads the voltage on the VOL/MICDET pin and
updates the digital volume control. (It overwrites the current value of the volume control.) The new volume
setting which has been applied due to a change of voltage on the volume control pin can be read on
page 0 / register 117, bits D6–D0. The 7-bit Vol ADC clock source can be selected on page 0 /
register 116, bit D6. The update rate can be programmed on page 0 / register 116, bits D2–D0 for this
7-bit SAR ADC.
The VOL/MICDET pin gain mapping is shown in Table 5-13.
Table 5-13. VOL/MICDET Pin Gain Mapping
VOL/MICDET PIN SAR OUTPUT
DIGITAL GAIN APPLIED
0
18 dB
1
17.5 dB
2
17 dB
:
35
0.5 dB
36
0.0 dB
37
–0.5 dB
:
89
–26.5 dB
90
–27 dB
91
–28 dB
:
125
–62 dB
126
–63 dB
127
Mute
28
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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| TLV320DAC3202 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:LOW POWER HIGH FIDELITY I2S INPUT HEADSET IC |
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