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SLAS659 – NOVEMBER 2009
If shutdown occurs due to an overcurrent condition, then the device requires a reset to re-enable the
output stage. Resetting can be done in two ways. First, the device master reset can be used, which
requires either toggling the RESET pin or using the software reset. If master reset is used, it resets all of
the registers. Second, a dedicated speaker power-stage reset can be used that keeps all of the other
device settings. The speaker power-stage reset is done by setting page 1 / register 32, bit D7 for SPKP
and SPKM. If the fault condition has been removed, then the device returns to normal operation. If the
fault is still present, then another shutdown occurs. Repeated resetting (more than three times) is not
recommended, as this could lead to overheating.
To minimize battery current leakage, the SPKVDD voltage level should not be less than the AVDD
voltage level.
The TLV320DAC3120 has a thermal protection (OTP) feature for the speaker drivers which is always
enabled to provide protection. If the device is overheated, then the output stops switching. When the
device cools down, the output resumes switching. An overtemperature status flag is provided as a
read-only bit on page 0 / register 3, bit D1. The OTP feature is for self-protection of the device. If die
temperature can be controlled at the system/board level, then overtemperature does not occur.
5.6.10 Audio Output-Stage Power Configurations
After the device has been configured (following a RESET) and the circuitry has been powered up, the
audio output stage can be powered up and powered down by register control.
These functions soft-start automatically. By using these register controls, it is possible to turn all four
stages on at the same time without turning two of them off.
See
Table 5-19 for register control of audio output stage power configurations.
Table 5-19. Audio Output Stage Power Configurations
Audio Output Pins
Desired Function
Page 1 / Register, Bit Value
HPOUT
Power-down HPOUT driver
Page 1 / register 31, bit D7 = 0
HPOUT
Power-up HPOUT driver
Page 1 / register 31, bit D7 = 1
SPKP / SPKM
Power-down class-D driver
Page 1 / register 32, bit D7 = 0
SPKP / SPKM
Power-up class-D driver
Page 1 / register 32, bit D7 = 1
5.7
CLOCK Generation and PLL
The TLV320DAC3120 supports a wide range of options for generating clocks for the DAC sections as well
as interface and other control blocks as shown in
Figure 5-16. The clocks for the DAC require a source
reference clock. This clock can be provided on a variety of device pins, such as the MCLK, BCLK, or
GPIO1 pins. The source reference clock for the codec can be chosen by programming the
CODEC_CLKIN value on page 0 / register 4, bits D1–D0. The CODEC_CLKIN can then be routed through
highly-flexible clock dividers shown in
Figure 5-16 to generate the various clocks required for the DAC and
the miniDSP section. In the event that the desired audio clocks cannot be generated from the reference
clocks on MCLK, BCLK, or GPIO1, the TLV320DAC3120 also provides the option of using the on-chip
PLL which supports a wide range of fractional multiplication values to generate the required clocks.
Starting from CODEC_CLKIN, the TLV320DAC3120 provides several programmable clock dividers to help
achieve a variety of sampling rates for the DAC and clocks for the miniDSP sections.
Copyright 2009, Texas Instruments Incorporated
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