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| 型號： | TLV320DAC3120IRHBR |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 24-BIT DAC, PQCC32 |
| 封裝： | 5 X 5 MM, PLASTIC, QFN-32 |
| 文件頁數(shù)： | 35/110頁 |
| 文件大小： | 1230K |
| 代理商： | TLV320DAC3120IRHBR |
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SLAS659 – NOVEMBER 2009
www.ti.com
Table 5-15. DRC HPF and LPF Coefficients
Coefficient
Location
HPF N0
C71 page 9 / registers 14 to 15
HPF N1
C72 page 9 / registers 16 to 17
HPF D1
C73 page 9 / registers 18 to 19
LPF N0
C74 page 9 / registers 20 to 21
LPF N1
C75 page 9 / registers 22 to 23
LPF D1
C76 page 9 / registers 24 to 25
The default values of these coefficients implement a high-pass filter with a cutoff at 0.00166 × DAC_fS,
and a low-pass filter with a cutoff at 0.00033 × DAC_fS.
The output of the DRC high-pass filter is fed to the processing block selected for the DAC channel. The
absolute value of the DRC-LPF filter is used for energy estimation within the DRC.
The gain in the DAC digital volume control is controlled by page 0 / registers 65 and 66. When the DRC is
enabled, the applied gain is a function of the digital volume-control register setting and the output of the
DRC.
The DRC parameters are described in sections that follow.
5.6.4.1
DRC Threshold
The DRC threshold represents the level of the DAC playback signal at which the gain compression
becomes active. The output of the digital volume control in the DAC is compared with the set threshold.
The threshold value is programmable by writing to page 0 / register 68, bits D4–D2. The threshold value
can be adjusted between –3 dBFS and –24 dBFS in steps of 3 dB. Keeping the DRC threshold value too
high may not leave enough time for the DRC block to detect peaking signals, and can cause excessive
distortion at the outputs. Keeping the DRC threshold value too low can limit the perceived loudness of the
output signal.
The recommended DRC threshold value is –24 dB.
When the output signal exceeds the set DRC threshold, the interrupt flag bits at page 0 / register 44,
bits D3–D2 are updated. These flag bits are sticky in nature, and are reset only after they are read back
by the user. The non-sticky versions of the interrupt flags are also available at page 0 / register 46, bits
D3–D2.
5.6.4.2
DRC Hysteresis
DRC hysteresis is programmable by writing to page 0 / register 68, bits D1–D0. These bits can be
programmed to represent values between 0 dB and 3 dB in steps of 1 dB. It is a programmable window
around the programmed DRC threshold that must be exceeded for disabled DRC to become enabled, or
enabled DRC to become disabled. For example, if the DRC threshold is set to –12 dBFS and the DRC
hysteresis is set to 3 dB, then if the gain compression in DRC is inactive, the output of the DAC digital
volume control must exceed –9 dBFS before gain compression due to the DRC is activated. Similarly,
when the gain compression in the DRC is active, the output of the DAC digital volume control must fall
below –15 dBFS for gain compression in the DRC to be deactivated. The DRC hysteresis feature prevents
the rapid activation and de-activation of gain compression in DRC in cases when the output of the DAC
digital volume control rapidly fluctuates in a narrow region around the programmed DRC threshold. By
programming the DRC hysteresis as 0 dB, the hysteresis action is disabled.
The recommended value of DRC hysteresis is 3 dB.
30
APPLICATION INFORMATION
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s): TLV320DAC3120
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